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參數(shù)資料
| 型號： | SSTUG32865ET/S |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 154K |
| 代理商： | SSTUG32865ET/S |
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SSTUG32865_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 August 2007
10 of 28
NXP Semiconductors
SSTUG32865
1.8 V DDR2-1G registered buffer with parity
functionality is not desired, then the CSGATEEN input can be hardwired to ground, in
which case, the set-up time requirement for DCSn would be the same as for the other Dn
data inputs.
The SSTUG32865 includes a parity checking function. The SSTUG32865 accepts a
parity bit from the memory controller at its input pin PARIN, compares it with the data
received on the Dn inputs (with either DCSn inputs active) and indicates whether a parity
error has occurred on its open-drain PTYERR pin (active LOW).
7.3 Functional differences to SSTU32864
The SSTUG32865 for its basic register functionality, signal denition and performance is
based upon the industry-standard SSTU32864, but provides key operational features
which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, DCS2, DCS3,
CSGATEEN)
As a means to reduce device power, the internal latches will only be updated when one or
more of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the
clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include
addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining
signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they
are independent of CS. The CS gating function can be disabled by tying CSGATEEN
LOW, enabling all internal latches to be updated on every rising edge of the clock.
7.3.2 Parity error checking and reporting
The SSTUG32865 incorporates a parity function, whereby the signal received on input pin
PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs.
The received parity bit is then compared to the parity calculated across these same inputs
by the register parity logic to verify that the information has not been corrupted. The 22
CS-gated input signals will be latched and re-driven on the rst clock, and any error will be
reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive
clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a
common signal pin for reporting the occurrence of a parity error during a valid command
cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive
clock cycles to allow the memory controller sufcient time to sense and capture the error
even. A LOW state on PTYERR indicates that a parity error has occurred.
7.3.3 Reset (RESET)
Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all
internal latches and all outputs will be driven LOW quickly except the PTYERR output,
which will be oated (and will normally default HIGH by their external pull-up).
Table 7.
Chip Select gating mode
Mode
Signal name
Description
Gating
CSGATEEN
HIGH
Registers only re-drive signals to the DRAMs when
Chip Select inputs are LOW.
Non-gating
CSGATEEN
LOW
Registers always re-drive signals on every clock cycle,
independent of the state of the Chip Select inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SSTUG32866 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G,518 | 功能描述:寄存器 1.8V REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTUG32866EC/G-T | 功能描述:寄存器 1.8V REG BUF/PARITY-DDR2-1G RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTUG32866EC/S | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
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