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參數(shù)資料
| 型號： | SSTUG32865ET/S |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 154K |
| 代理商： | SSTUG32865ET/S |
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1.
General description
The SSTUG32865 is a 1.8 V 28-bit 1 : 2 register specically designed for use on two rank
by four (2R
× 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUG32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it can be
congured for normal or high output drive strength, simply by tying input pin SELDR either
HIGH of LOW as needed. This allows use in different module designs varying from low to
high density designs by picking the appropriate drive strength to match net loading
conditions. Furthermore, the SSTUG32865 features two additional chip select inputs,
which allow more versatile enabling and disabling in densely populated memory modules.
Both added features (drive strength and chip selects) are fully backward compatible to the
JEDEC standard register.
The SSTUG32865 is packaged in a 160-ball, 12
× 18 grid, 0.65 mm ball pitch, thin prole
ne-pitch ball grid array (TFBGA) package, which, while requiring a minimum
9mm
× 13 mm of board space, allows for adequate signal routing and escape using
conventional card technology.
2.
Features
I 28-bit data register supporting DDR2
I Fully compliant to JEDEC standard for SSTUB32865
I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2
× SSTUB32864 or 2 × SSTUB32866)
I Parity checking function across 22 input data bits
I Parity out signal
I Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
I Exceeds SSTUB32865 JEDEC standard speed performance
I Supports up to 550 MHz clock frequency of operation
I Programmable for normal or high output drive
I Optimized pinout for high-density DDR2 module design
SSTUG32865
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G
RDIMM applications
Rev. 01 — 16 August 2007
Product data sheet
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSTUG32868ET/G | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA176 |
| SSTUP32866EC/S | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTV16857EC | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| SSTV16859DGG,118 | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO64 |
| SSTV16859BS,118 | SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTUG32866 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G,518 | 功能描述:寄存器 1.8V REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTUG32866EC/G-T | 功能描述:寄存器 1.8V REG BUF/PARITY-DDR2-1G RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTUG32866EC/S | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
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