參數(shù)資料
型號： SPC5200CBV400
廠商： Freescale Semiconductor
文件頁數(shù)： 67/72頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 400MHZ 272-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： MPC52xx
處理器類型： 32-位 MPC52xx PowerPC
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 托盤
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
7
1.1.4
Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to high-static voltage or
electrical fields. However, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages. Operational
reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND
or VCC). Table 7 gives package thermal characteristics for this device.
1.1.5
Power Dissipation
Power dissipation of the MPC5200B is caused by 3 different components: the dissipation of the internal or core digital logic
(supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD)
and the dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and
analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins
can not be given in general, but must be calculated by the user for each application case using the following formula:
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f
is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the
MPC5200B processor must not exceed the value, which would cause the maximum junction temperature to be exceeded.
Eqn. 2
Table 5. ESD and Latch-Up Protection Characteristics
Sym
Rating
Min
Max
Unit
SpecID
VHBM
Human Body Model (HBM)—JEDEC JESD22-A114-B
2000
—
V
D4.1
VMM
Machine Model (MM)—JEDEC JESD22-A115
200
—
V
D4.2
VCDM
Charge Device Model (CDM)—JEDEC JESD22-C101
500
—
V
D4.3
ILAT
Latch-up Current at TA=85
oC
positive
negative
+100
–100
—mA
D4.4
ILAT
Latch-up Current at TA=27
oC
positive
negative
+200
–200
—mA
D4.5
P
IO
P
IOint
N
M
∑
+
CVDD_IO
2
f
×
=
P
total
P
core
P
analog
P
IO
++
=
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