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參數(shù)資料
| 型號(hào)： | SP9842BS |
| 英文描述： | 8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
| 中文描述： | 8位八路，2象限乘法，BiCMOS工藝援 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大小： | 745K |
| 代理商： | SP9842BS |
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to strobe serial data into a 12–stage shift–register at
each rising clock edge. The first four serial bits contain
the address of the DAC to be updated, MSB first. The
next 8 bits contain the binary value to be loaded into
the desired DAC, again MSB first. After the 12th serial
bit is clocked in, the LOADH line can be strobed to
latch the 8 bits of data into the data holding register for
the desired DAC. The address bits feed a decoding
network which steers the LOADH pulse to the clock
input of the desired DAC data holding register. The
output of the 12th shift–register is also buffered and
brought out as the SERIAL DATA OUT (SDO),
which can be used to cascade multiple devices, or for
data verification purposes.
The address field is set up such that DAC A is
addressed at 0001 (binary). Address 0000(binary)
will not affect the operation of any channel, as this
combination is easily generated inadvertently at
power–up. Other no–operation addresses exist at
1001(binary) through 1111(binary). Another use for
no–operation addresses is to mask off updates of any
DAC channel in a multiple–part system with cas-
caded serial inputs and outputs. By sending a valid
address and data only to the desired channel, it is
possible to simplify the system hardware by driving
the LOADH pin at each part in parallel from a single
source.
Table 1
shows a register–level diagram of the
addresses, data, and the resulting operation.
A fourth control pin, PRESETL, can be used to
simultaneously preset all DAC data holding registers
to their mid–scale (80
) values. This will asynchro-
nously force all DAC outputs to buffer the voltages at
their respective inputs to their outputs with unity gain.
This feature is useful at power–up, as a simple resistor
to the supply and capacitor to ground can insure that
all DAC outputs start at a known voltage. It can also
be used to implement stand-alone (non–programmed)
applications, such as a unity gain octal cable driver.
Table 2
summarizes the operation of the four digital
control inputs.
The four digital control input pins have been
designed to accept TTL (0.8V to 2.0V minimum)
or full 5V CMOS input levels. Timing information
is shown in
Figure 4
. Serial data is fully clocked
into the shift–register after 12 clock rising edges,
subject to the described setup and hold times. After
the shift–register data is valid, the LOADH line
can be pulsed high to load data into the desired
DAC data register, which switches the DAC to the
new input code. The serial clock input should not
see a rising edge while the LOADH pulse is high
in order to prevent shift–register data from corrup-
tion during data register loading.
The serial clock and data input pins are designed to be
compatible as slaves under
National Semiconductor
's
Microwire and MicrowirePlus protocols and
under
Motorola
's SPI and QSPI protocols. In
some micro–controllers, the interface is completed by
programming a bit in a general–purpose I/O port as a
level, used to strobe the LOADH line at the DACs.
This is done in a manner similar to that used for
generating a CS signal, which is necessary when
driving some other Microwire peripherals.
Low Voltage Operation
At nominal V
, the CMOS switches used in the
DAC obtain sufficient drive to maintain an ON-
resistance much lower than the thin–film resistors.
This keeps the non–linear voltage–dependent portion
of their ON-resistances low, and guarantees both
excellent DAC linearity versus code, and low–distor-
tion multiplication of large–swinging AC inputs. The
devices in the op amp also receive sufficient drive to
guarantee the specified bandwidth and output drive
current. However, all circuits within the DACs are
quite "functional" at very low values of V
. By
reducing the reference voltages such that the maxi-
mum V
is near the target of V
-1.5V, the DACs
will provide better than 0.5LSB typical integral per-
formance for DC output voltages between 100mV
and V
-1.5V. Reducing the reference voltage actu-
ally aids the linearity of the DACs, even at nominal
V
. This occurs because the NMOS half of the
CMOS switches are more fully utilized at reference
voltages closer to ground, thus further reducing the
ON–resistance of the switches. Reference input cur-
rents are proportional to the reference voltages and
will also decrease with the reference voltages.
Plot 19
shows typical DC output linearity for V
(X)
set to 0.5V, with V
at 2.5, and then 3.5V. Note that
at 3.5V, the linearity is actually much better than the
±
0.25LSB typical performance at V
(X) = 1.625V
and V
= 5V. Similarly,
Plot 20
shows that this
performance level persists for V
= 4.5V and 5.5V,
with V
(X) set to 0.6V. The price paid for low voltage
operation is in op amp gain, bandwidth and es–
pecially current sinking at the DAC output.
Plots 17
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