參數(shù)資料
型號: SP9842BS
英文描述: 8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC
中文描述: 8位八路,2象限乘法,BiCMOS工藝援
文件頁數(shù): 17/32頁
文件大?。?/td> 745K
代理商: SP9842BS
283
tiple DAC applications without additional external
decoding logic.
The
SP9841/9842
consume only 65 mW from a
single +5V power supply. The
SP9841
is available in
24-pin plastic DIP and SOIC packages. The
SP9842
is available in a space–saving 20–pin SOIC package.
For applications requiring code–controlled output
polarity reversal regardless of the reference input level
(i.e. four–quadrant multiplication), please see the
SP9840/SP9843
product data sheet.
USING THE SP9841/9842
Theory of Operation
Each of the eight channels of the
SP9841/SP9842
can
be used for signal reconstruction, as a programmable
dc source, or as a programmable gain/attenuation
block, multiplying an ac reference input by factors of
0 to 1.992. The rugged, wideband output amplifiers
provide both current sink and source capability for dc
applications, even those driving difficult loads. The dc
source mode mimics the functionality of a program-
mable trimpot with the added benefit of a low imped-
ance buffered output. The amplifier's bandwidth and
high open–loop gain allow its use in programmable
gain applications where even a low distortion, high
resolution signal (such as audio) must be gated on and
off or gain–controlled over a –42 to +6dB range.
Each channel consists of a voltage–output DAC,
implemented using CMOS switches and thin–film
resistors in a inverted R–2R ladder configuration.
Each DAC drives the positive terminal of an op amp
+
8
DAC 1
R
R
V
IN
V
DAC
V
OUT
V
OUT
= 2 X V
DAC
when V
REF
L = 0V
= 2(D/256) X V
IN
= D/128 X V
IN
V
OUT
= D/128 X (V
IN
– V
REF
L) +V
REF
L
V
REF
L
Figure 1. DAC and Output Amplifier Circuit
configured for a non–inverting gain of 2 using equal
value thin–film feedback and gain–setting resistors.
Signal ground is the V
pin, the common reference
input return for the 8 DAC–op amp channels. As
shown in
Figure 1
, the DAC section can be thought of
as a potentiometer across V
(X) to V
. When this
potentiometer reaches its maximum output value of
255/256 times V
, the output will be 1+(R
/R
) or
2 times the value of V
(actually up to 1.9921875
times the input voltage, with V
tied to ground).
When the potentiometer is at its minimum value of 0/
256, the output will try to be 0V, again assuming V
REFL
is tied to ground.
The true relation between the dc levels at the V
IN
pin,
V
REFL
and the output can be described as:
V
OUT
= ((1 + R
FB
/R
G
) * (Data/256) * (V
IN
– V
REFL
)) + V
REFL
where Data is programmable from 0 to 255, and R
FB
= R
G
.
2.5
1.5
0
V
O
0
0.5
V
IN(X)
(Volts)
1.5
V
REF
L= 0V
D = FF
H
D = 80
H
D = 00
H
1.0
0.5
1.0
2.0
3.0
2.5
1.5
0
0.75
V
O
2.25
V
REF
L= 1.5V
V
IN(X)
(Volts)
D=FF
H
D = 80
H
D = 00
H
1.5
0.5
1.0
2.0
3.0
Figure 2. a) Single–Quadrant, and b) Two–Quadrant Operation
a)
b)
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