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參數(shù)資料
| 型號(hào)： | SP9841KS |
| 英文描述： | 8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
| 中文描述： | 8位八路，2象限乘法，BiCMOS工藝援 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大小： | 745K |
| 代理商： | SP9841KS |
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is requested, feedback within the op amp circuit
will force internal nodes to the rails, while the
output will remain saturated near this minimum
value. Non–saturated monotonic behavior returns
between 25mV and 100mV at the output, but full
open loop gain and linearity are not apparent until
the output voltage is nearly 100mV above the
negative supply. Applications which require good
linearity for codes near zero should drive the V
input at least 100mV above the ground pin, as this
insures that the output voltage will not go below
100mV for any legal input voltage. Two–quadrant
applications (programmable gain/attenuator) usually
bias V
up at system pseudoground, well above this
saturation region, and therefore maintain linearity
even at high attenuations (i.e. at code 1).
The allowable, useful values of V
(X) and V
are
limited if a legal output value is to be expected for all
input codes. At maximum gain (DAC code 255) V
is approximately equal to 2V
(X) – V
. By solving
this equation twice, once with V
set to 0V, and then
again with Vout set to V
–1.5V, the chart of
Figure
3a
results. This chart can be used to find the maximal
V
(X) voltage excursions for any given voltage
driven into V
REFL
. The upper line plots the maximum
voltage at V
mum voltage at V
(X) at each value of V
drive.
Normal operation would be for V
(X) anywhere
between the two lines. For example, assume a 4.75V
supply voltage, and that the DAC code is set to 255. If
V
is driven to 1.6V, V
(X) below 0.8V would
require the output amplifier to swing below ground.
V
(X) above 2.425V would require output voltages
greater than V
DD
– 1.5V, or 3.25V.
Figure 3b
shows the limits on V
when the mini-
mum V
is constrained to be greater than 100mV,
for extremely linear operation, even at DAC code
1. In this case, the lower line is 50mV above its
position in
Figure 3a
, except that below V
=
100mV, the minimum input voltage stays at
100mV. It should be noted that V
(X) can always
be driven to or slightly beyond the supply rails
without harm. Under such circumstances, the DAC
code can always be set to provide sufficient attenu-
ation to get an undistorted output.
Driving the Reference Inputs
The V
inputs exhibit a code–dependent input resis-
tance, as shown in the specifications. In general, these
inputs should be driven by an amplifier capable of
handling the specified load resistance and capaci-
tance. The reference inputs are useful for both ac and
dc input sources. However, series resistance into these
pins will degrade the linearity of the DAC. A series
resistance of 50 Ohms can cause up to 0.5LSB of
additional integral linearity degradation for codes
near full scale, due to the code–dependent input
current dropping across this error resistance. AC–
coupled applications should use the largest capacitor
value (lowest series resistance) which is practical, or,
use an external buffer to drive the inputs.
The DAC switches function in a break–before–make
manner in order to minimize current spikes at the
reference inputs. As previously noted, the reference
inputs can withstand driving voltages slightly beyond
the power supply rails without harm. The gain of 2 at
the op amps limits the choice of V
/V
combina-
tions if clipping is to be avoided at the higher codes.
Output Considerations
Each DAC output amplifier can easily drive 1Kohm
loads in parallel with 15pF at its rated slew rate. The
unique BiCMOS amplifier design also ensures stabil-
ity into heavily capacitive loads — up to 47,000pF.
Under these conditions, the slew rate will be limited by
the instantaneous current available for charging the
capacitance — the slew rate will be severely degraded,
and some damped ringing will occur. Especially
under heavy capacitive loading, a large, low imped-
ance local bypass capacitor will be required. A
0.047
μ
F ceramic in parallel with a low–ESR 2.2 to
10
μ
F tantalum are recommended for worst–case loads.
The amplifier outputs can withstand momentary
shorts to V
or ground. Continuous short circuit
operation can result in thermally induced damage,
and should be avoided.
If the input reference voltage is reduced to 0.6V, then
both the amplifier and DAC are functional at room
temperature at supply voltages as low as 2.5V. At V
= 2.7V, power dissipation is 9.3mW typical, with the
serial clock at 4MHz, or 7.0mW typical with the serial
clock gated off.
Interfacing to the SP9841/SP9842
A simple serial interface, similar to that used in a
74HC594 shift–register with output latch, has been
implemented in these products. A serial clock is used
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| SP9842KS | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC |
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