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參數(shù)資料
| 型號： | SP9604KS |
| 元件分類： | DAC |
| 英文描述： | QUAD, PARALLEL, WORD INPUT LOADING, 30 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| 封裝： | 0.350 INCH, PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | SP9604KS |
SP9604DS/03
SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter
Copyright 2000 Sipex Corporation
4
PIN ASSIGNMENTS
Pin 1 — V
OUT 4 — Voltage Output from DAC4.
Pin 2 — V
SS — –5V Power Supply Input.
Pin 3 — V
DD — +5V Power Supply Input.
Pin 4 — CLR — Clear. Gated with WR2 (pin 11).
Active low. Clears all DAC outputs to 0V.
Pin 5 — REF IN — Reference Input for DACs.
Pin 6 — GND — Ground.
Pin 7 — B1/B2 — Byte 1/Byte 2 — Selects Data
Input Format. A logic “1” on pin 7 selects the 12–bit
mode, and all 12 data bits are presented to the DAC(s)
unchanged;alogic“0”selectsthe8–bitmode,andthe
four LSBs are connected to the four MSBs, allowing
an 8–bit MSB–justified interface.
Pins 8 and 9 — A
0 & A1
— Address for DAC
Selection. A
1/A0 = 0/0 = DAC1; 0/1 = DAC2; 1/0 =
DAC3; 1/1 = DAC4.
Pin 10 — XFER — Transfer. Gated with WR2 (pin
11); loads all DAC registers simultaneously. Active
low.
Pin 11 — WR2 — Write Input 2 — In conjunction
with XFER (pin 10), controls the transfer of data
from the input registers to the DAC registers. In
conjunction with CLR (pin 4), the DAC registers are
forced to 1000 0000 0000 and the DAC outputs will
settle to 0V. Active low.
Pin 12 — WR1 — Write Input1 — In conjunction
with CS (pin 13), enables input register selection, and
controls the transfer of data from the input bus to the
input registers. Active low.
Pin 13 — CS — Chip Select — Enables writing data
to input registers and/or transferring data from input
bus to DAC registers. Active low.
Pin 14 — V
OUT1 — Voltage Output from DAC1.
Pin 15 — V
OUT2 — Voltage Output from DAC2.
Pin 16 — DB
11 — Data Bit 11; Most Significant Bit.
Pin 17 — DB
10 — Data Bit 10.
Pin 18 — DB
9 — Data Bit 9.
Pin 19 — DB
8 — Data Bit 8.
Pin 20 — DB
7 — Data Bit 7.
Pin 21 — DB
6 — Data Bit 6.
Pin 22 — DB
5 — Data Bit 5.
Pin 23 — DB
4 — Data Bit 4.
Pin 24 — DB
3 — Data Bit 3.
Pin 25 — DB
2 — Data Bit 2.
Pin 26 — DB
1 — Data Bit 1.
Pin 27 — DB
0 — Data Bit 0; LSB
Pin 28 — V
OUT3 — Voltage Output from DAC3.
PINOUT — 28–PIN PLASTIC DIP & SOIC
VOUT4
VSS
VDD
CLR
REF IN
GND
B1/B2
A0
A1
XFER
WR2
WR1
CS
VOUT1
VOUT3
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
VOUT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SP9604
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