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參數(shù)資料
| 型號(hào)： | SN74GTLP1394DR |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | Bus Exchanger |
| 中文描述： | 總線(xiàn)交換 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | SN74GTLP1394DR |
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SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286E
–
OCTOBER 1999
–
REVISED AUGUST 2001
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
protocol
Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and
transaction-layer information to an explicit address. The isochronous format broadcasts data based on channel
numbers rather than specific addressing. Isochronous packets are issued on the average of each 125
μ
s in
support of time-sensitive applications. Providing both asynchronous and isochronous formats on the same
interface allows both non-real-time and real-time critical applications on the same bus. The cable environment
’
s
tree topology is resolved during a sequence of events, triggered each time a new node is added or removed
from the network. This sequence starts with a bus reset phase, where previous information about a topology
is cleared. The tree ID sequence determines the actual tree structure, and a root node is dynamically assigned,
or it is possible to force a particular node to become the root. After the tree is formed, a self-ID phase allows
each node on the network to identify itself to all other nodes. During the self-ID process, each node is assigned
an address. After all the information has been gathered on each node, the bus goes into an idle state, waiting
for the beginning of the standard arbitration process.
The backplane physical layer shares some commonality with the cable physical layer. Common functions
include: bus state determination, bus access protocols, encoding and decoding functions, and synchronization
of received data to a local clock.
backplane features
25-, 50-, and 100-Mbps data rates for backplane environments
Live connection/disconnection possible without data loss or interruption.
Configuration ROM and status registers supporting plug and play
Multidrop or point-to-point topologies supported.
Specified bandwidth assignments for real-time applications
applicability and typical application for IEEE 1394 backplane
The 1394 backplane serial bus (BPSB) plays a supportive role in backplane systems, specifically GTLP,
FutureBus+, VME64, and proprietary backplane bus systems. This supportive role can be grouped into three
categories:
Diagnostics
–
–
–
Alternate control path to the parallel backplane bus
Test, maintenance, and troubleshooting
Software debug and support interface
System enhancement
–
–
–
–
Fault tolerance
Live insertion
CSR access
Auxiliary 2-bit bus with a 64-bit address space to the parallel backplane bus
Peripheral monitoring
–
Monitoring of peripherals (disk drives, fans, power supplies, etc.) in conjunction with another externally
wired monitor bus, such as defined by the Intelligent Platform Management Interface (IPMI).
The 1394 backplane physical layer (PHY) and the SN74GTLP1394 provide a cost-effective way to add
high-speed 1394 connections to every daughter card in almost any backplane. More information on the
backplane physical layer devices and how to implement the 1394 standard in backplane and cable applications
can be found at:
www.ti.com/sc/1394.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74GTLP1394PWR | Bus Exchanger |
| SN74HC4515DW | 4-To-16-Line Demultiplexer |
| CD74HC10H | Triple 3-input NAND Gate |
| CD74HC112NSR96 | FLIP-FLOP|DUAL|J/K TYPE|HC-CMOS|SOP|16PIN|PLASTIC |
| CD74HC11H | Triple 3-input AND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74GTLP1394DRE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394DRG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2B LVTTL to GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PW | 功能描述:轉(zhuǎn)換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PWE4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2-Bit LVTTL/GTLP Bus Xcvr Adj-Edge-Rate RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTLP1394PWG4 | 功能描述:轉(zhuǎn)換 - 電壓電平 2B LVTTL to GTLP Adj Edg RateBus Xcvr RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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