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參數(shù)資料
| 型號： | SN74ALVTH16601DGV |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 中文描述： | 2.5-V/3.3-V 18位通用總線收發(fā)器和三態(tài)輸出 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 196K |
| 代理商： | SN74ALVTH16601DGV |
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JULY 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is
low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
This device is fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
When V
CC
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16601 is characterized for operation over the full military temperature range of –55
°
C to
125
°
C. The SN74ALVTH16601 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OUTPUT
B
CLKENAB
X
OEAB
H
LEAB
X
CLKAB
A
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B0
B0
L
H
L
L
X
↑
↑
X
L
L
L
L
L
L
L
H
H
L
L
L
L or H
X
B0
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Output level before the indicated steady-state input conditions were
established
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| SN74ALVTH16646 | 2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs( 2.5V/3.3V16位總線收發(fā)器(三態(tài)輸出)) |
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| SN74ALVTH16821DGG | 2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ALVTH16601DL | 功能描述:通用總線函數(shù) 2.5/3.3V 18-Bit Univ Bus Trncvr W/3St Otp RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16601DLR | 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16601GR | 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16601VR | 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16821DL | 功能描述:觸發(fā)器 2.5/3.3V 20bit Univ RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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