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參數(shù)資料
| 型號： | SN54AC533FK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 中文描述： | 有三態(tài)輸出的8個透明D型鎖存器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 121K |
| 代理商： | SN54AC533FK |
SN54AC533, SN74AC533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS555A – NOVEMBER 1995 – REVISED MAY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
VOH
VOL
0 V
Input
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
×
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + 0.3 V
0 V
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
Open
TEST
S1
VCC
0 V
tw
VOLTAGE WAVEFORMS
Input
VOH – 0.3 V
50% VCC
50% VCC
50% VCC
VCC
VCC
50% VCC
50% VCC
50% VCC
50% VCC
VCC
50% VCC
50% VCC
50% VCC
50% VCC
VCC
50% VCC
50% VCC
50% VCC
tPHL
VOL
50% VCC
VOH
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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| SN54AC533J | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
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