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參數(shù)資料
| 型號： | SM5L3 |
| 廠商： | SHARP ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 164K |
| 代理商： | SM5L3 |
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4-Bit Single Chip Microcomputers
SM5L1/SM5L2/SM5L3
Microcomputer Data Sheet
21
Hardware Reset Function
The hardware reset function mode is activated two
instruction cycles after the falling edge from RESET pin.
When the RESET pin is changed from HIGH to LOW,
the pulse which is input by the OSCIN pin is counter 2
15
times after which the reset mode clears and the pro-
gram counter starts from address 0 on page 0.
The initialized status of the system after reset is
shown in Table 6.
The following reset functions are available:
The I/O port is set as an input port and the mode reg-
ister RD, RE and RF are cleared. The output only
port (P0) is cleared and output LOW.
The interrupt request flags (IFA, IFD) and the inter-
rupt enable flag (IME) are cleared and all interrupts
become disabled.
The program counter start from step 0 on page 0.
For activate reset function, when power is turned on,
you must connect a capacitor (0.1 F, TYP.) across the
RESET pin and GND.
NOTES:
1. In reset mode and at program start.
2. Undefined flags and registers should be initialized by software.
3. When all P1 pins (P10 to P13) level goes to HIGH, the SM5Lx is
programmed to reset operation (mask option).
Figure 26. Interrupt Timing Chart
INSTRUCTION
CYCLE
INTERRUPT PROCESSING ROUTINE
INTERRUPT
PROCESSING
ROUTINE
RTNI
INSTRUCTION
SYSTEM CLOCK
INTERRUPT
REQUEST FLAG
INTERRUPT
REQUEST FLAG
INT SIGNAL
INTERRUPT
ENABLE FLAG
5L1-26
Table 6. Reset Status
FLAG OR REGISTER, X
REGISTER
STATUS1
NOTES
PC
0
SP
Level 1
RAM
Undefined
2
ACC
Undefined
2
X register
Undefined
2
P0 - P2 output latch registers
0
Divider
0
IFA flag
0
IFD flag
0
IME flag
0
C flag
Undefined
2
BM, BL registers
Undefined
2
Register RD (bit 1)
Undefined
2
Register RD (bit 0)
0
Register RE (bit 2, 1, 0)
0
Register RF (bit 3, 2, 1, 0)
0
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