參數(shù)資料
型號(hào): SLA24C64-S-3
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
中文描述: 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝: PLASTIC, DSO-8
文件頁數(shù): 6/26頁
文件大小: 358K
代理商: SLA24C64-S-3
SLx 24C64
Semiconductor Group
6
Preliminary 1998-07-27
2
The SLx 24C64 device is a serial electrically erasable and programmable read only
memory (EEPROM), organized as 8192
×
8 bit. The data memory is divided into
256 pages. The 32 bytes of a page can be programmed simultaneously.
The device conforms to the specification of the 2-wire serial
I
2
C-Bus. Three chip select
pins allow the addressing of 8 devices on the
I
2
C-Bus. Low voltage design permits
operation down to 2.7 V with low active and standby currents. All devices have a
minimum endurance of 10
6
erase/write cycles.
The device operates at 5.0 V
±
10% with a maximum clock frequency of 400 kHz and at
2.7 ... 5.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V
type (
V
CC
= 4.5 … 5.5 V) with two temperature ranges for industrial and automotive
applications and as 3 V type (
V
CC
= 2.7 … 5.5 V) for industrial applications. The
EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as
chips.
Description
Figure 2
Block Diagram
DEC
X
EEPROM
Y DEC
Dout/ACK
SDA
SCL
IEB02525
Logic
Stop
Start/
Control
Logic
Chip Address
H.V. Pump
Programming
Control
Control
Logic
Serial
Logic
Address
Page Logic
CS0
CS1
CS2
SS
V
CC
V
WP
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