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參數(shù)資料
| 型號： | SLA24C64-S-3 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, DSO-8 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大小： | 358K |
| 代理商： | SLA24C64-S-3 |
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SLx 24C64
Semiconductor Group
13
Preliminary 1998-07-27
The erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for
speed enhancement in order to detect the end of the erase/write cycle. Please refer to
chapter 5.3
, Acknowledge Polling for further information.
5.3
During the erase/write cycle the EEPROM will not respond to a new command byte until
the internal write procedure is completed. At the end of active programming the chip
returns to the standby mode and the last entered EEPROM byte remains addressed by
the address counter. To determine the end of the internal erase/write cycle acknowledge
polling can be initiated by the master by sending a START condition followed by a
command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/
write cycle is not completed, the device will not acknowledge the transmission. If the
internal erase/write cycle is completed, the device acknowledges the received command
byte and the protocol activities can continue.
Acknowledge Polling
Figure 9
Flow Chart “Acknowledge Polling”
Internal Programming
Procedure
Send Start
Send CS-Byte
from EEPROM
received
Acknowledge
Next Operation
No
Yes
IED02131
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