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參數(shù)資料
| 型號(hào)： | SL15100ZIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SSCG 1PLL 2CH 8TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
Rev 1.8, August 10, 2007
Page 2 of 16
SL15100
Pin Configuration
8
SL15100
7
6
5
4
1
2
3
SSON#/FS
SSCLK2/REFCLK2
SSCLK1/REFCLK1
VSS
PD#/OE
XIN/CLKIN
XOUT
VDD
8-Pin TSSOP
Pin Description
Pin
Number
Pin Name
Pin Type
Pin Description
1
VDD
Power
Positive power supply.
2
XOUT
Output
Crystal or ceramic resonator output pin. Leave this pin unconnected
(floating) if external clock is used at Pin-3.
3
XIN/CLKIN
Input
Crystal, ceramic resonator or external clock input pin.
4
PD#/OE
Input
User Programmable PD# or OE control pin. Power Down (PD#-Active
Low): If PD#=0(Low), the device is powered down and both SSCLK and
REFOUT outputs are weakly pulled low to VSS. Output Enable (OE-
Active High): If OE=1(High), the SSCLK and REFOUT outputs are
enabled.
PD# or OE is weakly pulled high to VDD.
5
VSS
Power
Power supply ground.
6
SSCLK1 or
REFCLK1
Output
This pin can be programmed as SSCLK1 or REFCLK1.
7
SSCLK2 or
REFCLK2
Output
This pin can be programmed as SSCLK2 or REFCLK2.
8
SSON#/FS
Input
Programmable SSON# or Frequency Select (FS) Control pin. If SSCG#
function is programmed: Spread-on=0(Low) or Spread-off=1(High). If FS
function is programmed: The clock frequencies can be switched between
two sets of frequencies as programmed.
SSON# or FS is weakly pulled low to VSS.
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