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參數(shù)資料
| 型號： | SK10EP111 |
| 廠商： | Semtech Corporation |
| 英文描述： | Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver |
| 中文描述： | 低電壓1:10差動ECL / PECL的/ HSTL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 100K |
| 代理商： | SK10EP111 |
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SK10EP111
Low-Voltage 1:10 Differential
ECL/PECL/HSTL Clock Driver
Features
100 ps Part-to-Part Skew
35 ps Output-to-Output Skew
Differential Design
VBB Output
Low Voltage VEE Range of –2.375 to –3.8V for ECL
Low Voltage VCC Range of +2.375 to +3.8V for PECL and HSTL
75 K
Input Pulldown Resistors
ECL/PECL Outputs
Description
The SK10EP111 is a low skew 1-to-10 diffferential driver, designed
with clock distribution in mind. It accepts two clock sources into an
input multiplexer. The ECL/PECL input signals can be either
differential or single-ended if the VBB output is used. HSTL inputs
can be used when the EP111 is operating under PECL conditions.
The selected signal is fanned out to 10 identical differential outputs.
The SK10EP111 is specifically designed, modeled, and produced
with low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and characterization is
used to determine process control limits that ensure consistent tpd
distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary
that both sides of the differential output are terminated into 50
,
even if only one side is being used. In most applications, all ten
differential pairs will be used and therefore terminated. In the case
where fewer than ten pairs are used, it is necessary to terminate at
least the output pairs on the same package side as the pair(s) being
used on that side in order to maintain minimum skew. Failure to do
this will result in small degradations of propagation delay (on the
order of 10–20 ps) of the output(s) being used which, while not
being catastrophic to most designs, will mean a loss of skew margin.
The SK10EP111, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the EP111
to be used for high performance clock distribution in +3.3V or +2.5V
systems. Designers can take advantage of the EP111’s performance
to distribute low skew clocks across the backplane or the board. In
a PECL environment, series or Thevenin line terminations are
typically used as they require no additional power supplies.
October 4, 1999
32 Lead
LQFP Package
Preliminary Information
This document contains information on a new product. The
parametric information, although not fully characterized, is the result
of testing initial devices.
Low-Voltage 1:10
Differential ECL/PECL/HSTL
Clock Driver
CLK0
CLK0*
CLK1
CLK1*
CLK_SEL
Q0:9
Q0*:9*
10
0
1
VBB
Pinout
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Pin Names
Function
VCC0
Q7
Q7*
Q8
Q8*
Q9
Q9*
VCC0
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCC0
Q2*
Q2
Q1*
Q1
Q0*
Q0
VCC0
V
C
C
C
V
C
C
V
Q
Q
Q
Q
Q
Q
Q
Q
SK10EP111
24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8
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