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參數(shù)資料
| 型號(hào)： | SK100LVE111E |
| 廠商： | Semtech Corporation |
| 英文描述： | CRYSTAL 25.0 MHZ 20PF SMD |
| 中文描述： | 低電壓1:9差動(dòng)ECL / PECL的時(shí)鐘使能輸入驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 150K |
| 代理商： | SK100LVE111E |
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SK10LVE111E
SK100LVE111E
Low Voltage 1:9 Differential ECL/PECL
Clock Driver with Enable Input
Features
200 ps Part-to-Part Skew
50 ps Output-to-Output Skew
Differential Design
V
BB
Output
Enable Input
Voltage and Temperature Compensated Outputs
Low Voltage V
EE
Range of –3,0 to –3.8V
75K
Internal Pulldown Resistors
Fully Compatible with Motorola MC100LVE111
Specified Over Industrial Temperature Range:
–40C to 85C
ESD Protection of >2000V
Available in 28-pin PLCC Package
Description
The SK10/1000LVE111E is a low skew 1-to-9 differential driver
designed with clock distribution in mind. The SK10/
100LVE111E’s function and performance are similar to the
SK100E111, with the added feature of low voltage operation.
It accepts one signal input which can be either differential or
single-ended if the V
BB
output is used. The signal is fanned
out to 9 identical differential outputs. An enable input is also
provided. A High disables the device by focing all Q outputs
Low and all Q* outputs High.
The device is specifically designed, modeled, and produced
with low skew as the key goal. Optimal design and layout serve
to minimize gate-to-gate skew within a device, and
characterization is used to determine process control limits that
ensure consistent tpd distributions from lot to lot. The net result
is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary
that both sides of the differential output are terminated into 50
,
even if only one side is being used. In most applications, all
nine differential pairs will be used and therefore terminated. In
the case where fewer than nine pairs are used, it is necessary
to terminate at least the output pairs on the same package
side as the pair(s) being used on that side in order to maintain
minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10–20ps)
October 6, 1999
28 Pin
PLCC Package
Preliminary Information
This document contains information on a new product. The parametric
information, although not fully characterized, is the result of testing
initial devices.
Low Voltage 1:9 Differential
ECL / PECL Clock Driver
of the output(s) being used which, while not being
catastrophic to most designs, will mean a loss of
skew margin.
The SK10/100LVE111E, as with most other ECL
devices, can be operated from a positive VCC
supply in PECL mode. This allows the LVE111E
to be used for high performance clock distribution
in +3.3V systems. Designers can take advantage
of the LVE111E’s performance to distribute low
skew clocks across the backplane or the board.
In a PECL environment, series or Thevenin line
terminations are typically used as they require no
additional power supplies. For systems
incorporating GTL, parallel termination offers the
lowest power by taking advantage of the 1.2V
supply as a terminating voltage.
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