
SiS5595 PCI System I/O Chipset
Preliminary V2.0 Nov. 2, 1998
Silicon Integrated Systems Corporation
iv
Figures
FIGURE 1.2-1 FUNCTIONAL BLOCK DIAGRAM .................................................... 4
FIGURE 2.1-1 PIN ASSIGNMENT (TOP VIEW) ...................................................... 6
FIGURE 3.1-1 PCI ISA DELAY TRANSACTION.................................................... 10
FIGURE 3.1-2 START FRAME TIMING WITH SOURCE SAMPLED A LOW PULSE
ON SMI# .......................................................................................... 13
FIGURE 3.1-3 STOP FRAME TIMING WITH HOST USING 17 SIRQ# SAMPLING
PERIOD ........................................................................................... 13
FIGURE 3.2-1 GLOBAL SYSTEM STATE DIAGRAM............................................ 16
FIGURE 3.2-2 WAKE UP EVENTS IN S1 / S2....................................................... 18
FIGURE 3.2-3 5595'S TIMING DIAGRAM IN S2 STATE ....................................... 18
FIGURE 3.2-4 NORTH BRIDGE/5595'S TIMING DIAGRAM IN S3 STATE ........... 19
FIGURE 3.2-5 STPCLK# THROTTLING & PERFORMANCE................................ 22
FIGURE 3.2-6 PROCESSOR POWER STATE DIAGRAM..................................... 23
FIGURE 3.2-7 STPCLK# SOURCE ....................................................................... 24
FIGURE 3.2-8 THERMAL DETECTION LOGIC..................................................... 25
FIGURE 3.2-9 SCI / SMI# EVENTS OVERVIEW.................................................. 27
FIGURE 3.2-10 GENERAL PURPOSE TIMER LOGIC.......................................... 28
FIGURE 3.2-11 GPIO LOGIC ................................................................................ 29
FIGURE 3.4-1 USB SYSTEM BLOCK DIAGRAM.................................................. 38
FIGURE 3.5-1 DATA ACQUISITION MODULE BLOCK DIAGRAM ....................... 39
FIGURE 3.6-1 RTC MODULE BLOCK DIAGRAM.................................................. 42
FIGURE 3.6-2 ADDRESS MAP OF THE STANDARD BANK................................. 43
FIGURE 3.6-3 BLOCK DIAGRAM OF RTC............................................................ 44
FIGURE 3.7-1 TYPICAL TIMING SEQUENCE ON THE POWER CONTROL
RELATED SIGNALS ...................................................................... 45
FIGURE 3.7-2 POWER UP REQUEST EVENTS................................................... 47
FIGURE 3.7-3 POWER BUTTON ON EVENT ....................................................... 47
FIGURE 3.7-4 RING UP EVENT............................................................................ 48
FIGURE 3.7-5 POWER MANAGE EVENT 1.......................................................... 49
FIGURE 3.7-6 POWER MANAGE EVENT 0.......................................................... 49
FIGURE 3.7-7 POWER DOWN REQUEST EVE.................................................... 50
FIGURE 3.9-1 INTERRUPT ROUTER IRX............................................................ 61
FIGURE 3.10-1 TIMING SEQUENCE FOR POWER-ON PROCESS..................... 62
FIGURE 3.10-2 TIMING FOR GENERATING INIT#/CPURST#............................. 62
FIGURE 5-1 BLOCK DIAGRAM FOR GENERATING CORE FREQUENCY....... 78
FIGURE 8.1-1 SiS5595 INTERNAL POWER PLANES........................................ 198
FIGURE 8.5-1 DMA CYCLES.............................................................................. 204
FIGURE 8.5-2 THE AC TIMING DIAGRAM OF PCI TO ISA BUS CYCLES......... 206
FIGURE 8.5-3 MISCELLANEOUS TIMING.......................................................... 209
FIGURE 9.2-1 SiS5595 PACKAGE SPECIFICATION.......................................... 209