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參數(shù)資料
| 型號(hào)： | SIS5595 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Pentium PCI System I/O Chipset |
| 中文描述： | 奔騰的PCI系統(tǒng)I / O芯片 |
| 文件頁(yè)數(shù)： | 18/216頁(yè) |
| 文件大小： | 2208K |
| 代理商： | SIS5595 |
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SiS5595 PCI System I/O Chipset
Preliminary V2.0 Nov. 2, 1998 12 Silicon Integrated Systems Corporation
continue to think it is communicating with a standard DMA controller. The SiS5595 is the
DMA Master and the protocol is as follows:
1) When the CPU Bridge attempts to read/write a legacy DMA register, a PCI I/O cycle will
be initiated on the PCI bus with a legacy DMA address. The SiS5595 will take control of
this cycle by driving DEVSEL# active, asserting PHOLD# and issuing a PCI retry to
terminate this cycle.
2) When granted the PCI bus, the SiS5595 will run up to 4 PCI I/O read/write cycles. The
specific I/O addresses for each legacy DMA address are remappable. The purpose of
these read/writes is to return/send the individual channel read/write information. DMA
Slave devices must only respond to the slave address assigned to them and not any
legacy DMA address.
3) At the end of the last read/write the SiS5595 will set an internal flag indicating the
completion and will de-assert PHOLD# and wait for the retried PCI I/O read/write from
the CPU bridge.
The PCI I/O read/write will be retried. If it was a read, the SiS5595 will return the data. If it
was a write, the SiS5595 will simply terminate the cycle. Then the SiS5595 will reset the
internal flag.
3.1.3 PC/PCI DMA
SiS5595B supports one PC/PCI PDMAREQ0#/PDMAGNT0# pairs. PCI devices plugged in
the PCI slot may initiate PC/PCI DMA transfer cycles through the PDMAREQ0#/
PDMAGNT0# pair. For DMA operation, three types of transfer cycles are supported:
Memory-to-I/O, I/O-to-Memory and Verify. SiS5595B also supports ISA master operation
through PC/PCI DMA channels, on which a PCI device may request the PCI bus through the
PDMAREQ0#/PDMAGNT0# pair. Each of the seven DMA channels can be individually
programmed to be in Legacy, DDMA or PC/PCI DMA mode. Care must be taken to ensure
only one of the three operation modes is enabled for a particular DMA channel. The legacy
8237 compatible registers will be used to control the operation of PC/PCI DMA, for software
backward compatibility.
3.1.4 SERIAL IRQ (SIRQ)
The Serial IRQ provides a mechanism for communicating IRQ status between ISA legacy
components, PCI components, and PCI system controllers. A serial interface is specified that
provides a means for transferring IRQ and/or other information from one system component
to a system host controller. A transfer, called a serial IRQ cycle, consists of three frame
types: one Start Frame, several IRQ/Data Frames, and one Stop Frame. This protocol uses
the PCI clock as its clock source and conforms to the PCI bus electrical specification.
3.1.4.1 Timing Diagrams For Serial IRQ Cycle
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