參數(shù)資料
型號(hào)： SII0680A
元件分類(lèi)： 存儲(chǔ)控制器/管理單元
英文描述： IDE COMPATIBLE, CD ROM CONTROLLER, PQFP144
封裝： LQFP-144
文件頁(yè)數(shù)： 18/34頁(yè)
文件大?。?/td> 280K
代理商： SII0680A
SiI 0680A Data Sheet Revision 1.31-1
25
Subject to change without notice
Primary channel interrupt request is an input signal used to generate the PCI_INTA_N output. This input should have a
10k pull-down resistor connected to it.
IDE1 I/O Ready
Pin Name: IDE1_IORDY
Pin Number: 76
The Secondary Channel Drive Channel’s In itiator Ready is an active high input. It indicates that the ATA disk drive has
-up resistor is recommended. This signal is defined as DSTROBE in
Ultra DMA read mode to read data from the currently selecte d drive attached to the secondary channel. This signal is also
defined as DDMARDY_N in Ultra DMA write mode.
IDE1 External Bias Circuit
Pin Name: IDE1_AT_REXT
Pin Number: 77
IDE1_AT_REXT is an analog pin for connection to an external bias circuit. This pin is sensitive to noise and must be routed
carefully. Keep the trace length on this pin as short as possible and away from any sources of noise.
IDE1 DMA Request
Pin Name: IDE1_DMARQ
Pin Number: 78
This signal is used in a handshake manner with IDE1_DMACK_N and shall be asserted high by the currently selected drive
attached to the secondary IDE/ATA channel when it is ready to transfer data to or from the host. . This pin should have a 5.6
K pull-down resistor connected to it.
IDE1 Disk Reset
Pin Name: IDE1_RST_N
Pin Number: 79
Disk Reset is an active low output which signals the IDE/ATA drive to initialize its control register. IDE1_RST_N is a
buffered version of the PCI_RST_N input. It can also be generated by programming the SiI 0680A register, and connects
directly to the ATA connector. IDE1_RST_N asserts reset to the secondary ATA channel.
3.3.3 PCI 33MHz 32-bit Section
PCI Address and Data
Pin Names: PCI_AD[31..0]
Pin Numbers: 81~86, 89, 90, 93~97, 100~102, 115~117, 120~124, 126, 127, 130~135
Address and Data buses are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed
by one or more data phases. PCI supports both read and write bursts. The address phase is the first clock cycle in which
PCI_FRAME_N signal is asserted. During the address phase, PCI_AD[31:0] contain a physical address (32 bits). For I/O,
this can be a byte address. For configuration and memory it is a DWORD address. During data phases, PCI_AD[7:0]
contain the least significant byte (LSB) and PCI_AD[31:24] contain the most significant byte (MSB). Write data is stable and
valid when PCI_IRDY_N is asserted; read data is stable and valid when PCI_TRDY_N is asserted. Data is transferred
during those clocks where both PCI_IRDY_N and PCI_TRDY_N are asserted.
PCI Command and Byte Enables
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