參數(shù)資料
型號(hào)： SII0680A
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： IDE COMPATIBLE, CD ROM CONTROLLER, PQFP144
封裝： LQFP-144
文件頁數(shù)： 16/34頁
文件大?。?/td> 280K
代理商： SII0680A
SiI 0680A Data Sheet Revision 1.31-1
23
Subject to change without notice
Pin Names: IDE0_CBLID_N
Pin Numbers: 38
IDE0_CBLID_N (Cable Detect) determines the type of cable attached to the primary channel. In general, a low on this pin
indicates that a 40 conductor cable is attached. A high indicates that an 80 conductor cable is attached. Refer to the
ATA/ATAPI-6 Specification for complete details.
IDE0 Interrupt Request
Pin Name: ID E0_INTRQ
Pin Number: 39
Primary channel interrupt request is an input signal used to generate the PCI_INTA_N output. This input should have a
10k pull-down resistor connected to it.
IDE0 I/O Ready
Pin Name: IDE0_IORDY
Pin Number: 40
The Primary channel drive I/O ready is an active high input. It indicates that the IDE/ATA disk drive has completed the
-up resistor is recommended. This signal is defined as DSTROBE in Ultra DMA read
mode to read data from the currently selected drive to the primary channel. This signal is also defined as DDMARDY_N in
Ultra DMA write mode.
IDE0 External Bias Circuit
Pin Name: IDE0_AT_REXT
Pin Number: 41
IDE0_AT_REXT is an analog pin for connection to an external bias circuit. This pin is sensitive to noise and must be routed
carefully. Keep the trace length on this pin as short as possible and away from any sources of noise.
IDE0 DMA Request
Pin Name: IDE0_DMARQ
Pin Number: 42
This signal is used in a handshake manner with IDE0_DMACK_N, and shall be asserted high by the currently selected
drive attached to the primary IDE/ATA Channel when it is ready to transfer data to or from the host. This pin should have a
5.6 K pull-down resistor connected to it.
IDE0 Disk Reset
Pin Name: IDE0_RST_N
Pin Number: 43
IDE0 Disk Reset is an active low output which signals the IDE/ATA drive to initialize its control register. IDE0_RST_N is a
buffered version of the PCI_RST_N input. It can also be generated by programming the SiI 0680A register and connects
directly to the ATA connector. IDE0_RST_N asserts reset to the primary IDE/ATA channel.
3.3.2 IDE/ATA Secondary Channel
IDE1 Disk Data Bus
Pin Names: IDE1_DD[15..0]
Pin Numbers: 63, 60, 59, 58, 57, 56, 55, 54, 53, 50, 49, 48, 47, 46, 45, 44
Disk Data bits 0 through 15 are the 16-bit bi-directional data bus, which connects to the IDE/ATA device(s). IDE1_DD[15:0]
are data signals to the secondary channel. IDE1_DD[7:0] defines the low data byte while IDE1_DD[15:8] defines the high
data byte of this 16-bits data register. The data bus is normally in a high impedance state and is driven by the SiI 0680A
during the IDE1_DIOW_N command pulse in either single/multi -word DMA mode, or valid at every edge of IDE1_DIOR_N
(HSTROBE) or IDE1_IORDY (DSTROBE) in Ultra DMA mode. IDE1_DD07 is a multifunction pin, which allows a host to
recognize the absence of an ATA/ATAPI device at power-
-down resistor is
recommended to be connected to this pin.
IDE1 Chip Select
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