參數(shù)資料
型號(hào)： SI5369C-C-GQ
廠商： SILICON LABORATORIES
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 346 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
封裝： 14 X 14 MM, ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù)： 74/84頁(yè)
文件大?。?/td> 870K
代理商： SI5369C-C-GQ
76
Preliminary Rev. 0.4
77
78
CKOUT3+
CKOUT3–
OMULTI
Clock Output 3.
Differential clock output. Output signal format is selected by
SFOUT3_REG
register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
82
83
CKOUT1–
CKOUT1+
OMULTI
Clock Output 1.
Differential clock output. Output signal format is selected by
SFOUT1_REG
register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
87
88
FS_OUT–
FS_OUT+
OMULTI
Frame Sync Output.
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG reg-
ister bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision Clock
Family Reference Manual.
90
CMODE
I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the device.
0=I2C Control Mode.
1 = SPI Control Mode.
This pin must be tied high or low.
92
93
CKOUT2+
CKOUT2–
OMULTI
Clock Output 2.
Differential clock output. Output signal format is selected by
SFOUT2_REG
register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
97
98
CKOUT4–
CKOUT4+
OMULTI
Clock Output 4.
Differential clock output. Output signal format is selected by
SFOUT4_REG
register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Table 10. Si5369 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note:
Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
相關(guān)PDF資料
PDF描述
SI5369D-C-GQ 243 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
SI5369D-C-GQR 243 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
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SI5375B-A-GL 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA80
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5369C-C-GQR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Lo Loop BW Clk Multi Jitter Attn 4In/5Out RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
Si5369D-C-GQ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 LW LOOP BW AR CLK MULT/JITTER 4IN 5OUT RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SI5369D-C-GQR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Lo Loop BW Clk Multi Jitter Attn 4In/5Out RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
Si5369-EVB 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 SI5369 DEV KIT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
Si5374B-A-BL 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Quad DSPLL Jittr Clk Low loop BW 8In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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