參數(shù)資料
型號(hào): SI5369C-C-GQ
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 346 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
封裝: 14 X 14 MM, ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁數(shù): 70/84頁
文件大?。?/td> 870K
代理商: SI5369C-C-GQ
72
Preliminary Rev. 0.4
6. Pin Descriptions: Si5369
Table 10. Si5369 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1, 2, 4, 20,
22, 23, 24,
25, 37, 47,
48, 50, 51,
52, 53, 56,
66, 67, 72,
73, 74, 75,
80, 85, 95
NC
No Connect.
These pins must be left unconnected for normal operation.
3
RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are dis-
abled during reset. The part must be programmed after a reset
or power-on to get a clock output. See Family Reference Man-
ual for details.
This pin has a weak pull-up.
Note:
Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
31
30
29
28
27
26
32
64
61
62
63
57
58
59
60
50
51
52
53
54
55
56
49
NC
GND
C2B
GND
C1B
C3B
XA
XB
VDD
CK
IN
3+
CKIN3
RA
TE0
CK
IN
1+
CK
IN1
CK
IN
2+
CK
IN2
RA
TE1
CK
IN
4+
CK
IN4
LOL
SDI
NC
A1
A0
GND
VDD
SDA_SDO
SCL
C2A
C1A
CS1_C4A
NC
GND
CKO
U
T3
+
CMOD
E
CKO
U
T3
NC
CKO
U
T1
+
CKO
U
T1
FS
_OUT
+
FS
_OUT
VDD
CKO
U
T2
+
CKO
U
T2
NC
CKO
U
T4
+
NC
CKO
U
T4
17
20
19
18
24
23
22
21
25
74
73
72
71
70
69
68
67
66
65
75
100
89
90
91
92
93
94
95
96
97
98
99
76
77
78
79
80
81
82
83
84
85
86
87
88
RST
NC
VDD
GND
CS0_C3A
GND
NC
GN
D
VD
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
VDD
A2_SS
GND
NC
VDD
NC
VDD
NC
Si5369
GND PAD
INT_ALM
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