參數(shù)資料
型號： SI5315B-C-GMR
廠商： Silicon Laboratories Inc
文件頁數(shù)： 7/54頁
文件大?。?/td> 0K
描述： IC CLOCK MULT 8KHZ-125MHZ 36QFN
應(yīng)用說明： SI5315/17 Crystal Selection AppNote
標(biāo)準(zhǔn)包裝： 250
系列： DSPLL®
類型： 時鐘/頻率倍增器，抖動衰減器，多路復(fù)用器
PLL： 無
主要目的： 以太網(wǎng)，SONET/SDH/PDH，電信
輸入： CML，CMOS，LVDS，LVPECL
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 125MHz
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 帶卷 (TR)
Si5315
Rev. 1.0
15
3. System Level Overview
The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous
Ethernet* line card timing applications.
*Note: The Si5315 supports SyncE EEC options 1 and 2 when paired with a timing card that implements the required wander
filtering and Stratum 3 compliant reference clock. For detailed information, refer to “AN420: SyncE and IEEE 1588: Sync
Distribution for a Unified Network”.
The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous
Ethernet line card timing applications. The device accepts two clock inputs ranging from 8 kHz to 644.53 MHz and
generates two equal frequency, low jitter clock outputs ranging from 8 kHz to 644.53 MHz. For ease of use, the
Si5315 is pin controlled to enable simple device configuration of frequency plans, PLL loop bandwidth, and input
clock selection. The DSPLL locks to one of two input reference clocks and provides over 200 frequency
translations to synchronize output clocks for Ethernet, SONET/SDH, and PDH line cards. The Si5315 implements
internal state machines to control hitless switching between input clocks and holdover. Status alarms, loss of signal
(LOS) and loss of lock (LOL) are provided on output pins to indicate a change in device status.
This device is designed for systems with line cards that are synchronized to a redundant, centralized telecom or
Ethernet backplane. The Si5315 synchronizes to backplane clocks and generates a multiplied, jitter attenuated
Ethernet/SONET/SDH clock or PDH clock. A typical system application is shown in Figure 6. The Si5315
translates a 19.44 MHz clock from the telecom backplane to an Ethernet or SONET/SDH clock frequency to the
PHY and filters the jitter to ensure compliance with related ITU-T and Telcordia standards.
Figure 6. Typical Si5315 Application
Telecom
or
Ethernet
Backplane
Wander Filtering
Hitless Switching
Holdover
Network Sync
PLL
8 kHz
19.44 MHz
25 MHz
Network
Synchronization
A
B
BITS A
L
in
e
R
e
c
o
v
e
re
d
T
im
in
g
BITS B
10G LAN / WAN
SyncE Line Card
Line
Recovered
Clocks
155.52 MHz
156.25 MHz
161.1328125 MHz
10GbE
PHY
Si5315
Tx Timing Path
Rx Timing Path
8 kHz
19.44 MHz
25 MHz
Jitter Filtering
Hitless Switching
Frequency Translation
10GbE
PHY
A
B
Redundant
Timing Cards
Multi-Port
SONET / SDH / PDH Line Card
Line
Recovered
Clocks
77.76 / 155.52 MHz
1.544 / 2.048 MHz
OC-3 / 12
Si5315
Tx Timing Path
Rx Timing Path
8 kHz
19.44 MHz
25 MHz
Jitter Filtering
Hitless Switching
Frequency Translation
A
B
T1 / E1
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參數(shù)描述
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