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參數(shù)資料
| 型號： | SI5110-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99LFBGA |
| 標準包裝： | 168 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應商設備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Si5110
30
Rev. 1.5
J8
TXCLKDSBL
I
LVTTL
High-Speed Transmit Clock Disable.
When this input is high, the output driver for TXCLK-
OUT is disabled. In applications that do not require the
output data clock, the output clock driver should be
disabled to save power.
Note: This input has an internal pulldown.
E1
F1
TXCLKOUT+,
TXCLKOUT–
High-Speed Transmit Clock Output.
The high-speed clock output, TXCLKOUT, is gener-
ated by the PLL in the transmit clock multiplier unit. Its
frequency is nominally 16 times or 32 times the
selected reference source.
G9
H9
G10
H10
J9
K9
J10
K10
TXDIN3+,
TXDIN3–
TXDIN2+,
TXDIN2–
TXDIN1+,
TXDIN1–
TXDIN0+,
TXDIN0–
ILVDS
Differential Parallel Transmit Data Input.
The 4-bit data word present on these pins is multi-
plexed into a high-speed serial stream and output on
TXDOUT. The bit order for transmit multiplexing is
selected by the TXMSBSEL input. The data on
TXDIN[3:0] is clocked into the device by the rising
edge of TXCLK4IN.
H1
J1
TXDOUT+,
TXDOUT–
OCML
Differential High-Speed Transmit Data Output.
The 4-bit word input on TXDIN[3:0] is multiplexed into
a high-speed serial stream that is output on the TXD-
OUT pins. The bit order for transmit multiplexing is
selected by the TXMSBSEL input. The TXDOUT out-
puts are updated by the rising edge of TXCLKOUT.
K4
TXLOL
O
LVTTL
Transmit CMU Loss-of-Lock.
The TXLOL output is asserted (low) when the CMU is
not phase locked to the selected reference source or if
REFCLK is not present.
H4
TXMSBSEL
I
LVTTL
Transmit Data Bus Bit Order Select.
This input determines the order in which data bits
recovered on the TXDIN[3:0] bus are transmitted on
the high-speed serial output TXDOUT.
For TXMSBSEL = 0, data on TXDIN0 is transmitted
first followed by TXDIN1 through TXDIN3.
For TXMSBSEL = 1, TXDIN3 is transmitted first fol-
lowed by TXDIN2 through TXDIN0.
Note: This input has an internal pulldown.
K3
TXREXT
Transmitter External Bias Resistor.
This resistor is used by the transmitter circuitry to
establish bias currents within the device. This pin must
be connected to GND through a 3.09 k
1resistor.
Pin
Number(s)
Name
I/O
Signal Level
Description
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