- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9967 > SI5100-H-GL (Silicon Laboratories Inc)IC TXRX SONET/SDH LP HS 195PBGA PDF資料下載
參數(shù)資料
| 型號： | SI5100-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 195PBGA |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 195-LBGA |
| 供應(yīng)商設(shè)備封裝： | 195-BGA（15x15） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Si5100
Rev. 1.5
31
D12
RXMSBSEL
I
LVTTL
Receive Data Bus Bit Order Select.
This determines the order of the received data
bits on the output bus.
When RXMSBSEL is set low, the first bit
received is output on RXDOUT0 and the follow-
ing bits are output in order on RXDOUT1
through RXDOUT15 (RXDOUT1 through
RXDOUT3 if MODE16 = 0). When RXMSBSEL
is set high, the first bit received is output on
RXDOUT15 (RXDOUT3) and the following bits
are output in order on RXDOUT14 (RXDOUT2)
through RXDOUT0.
Note: This input has an internal pulldown.
C11
RXREXT
Receiver External Bias Resistor.
This resistor is used by the receiver circuitry to
establish bias currents within the device. This pin
must be connected to GND through a 3.09 k
1resistor.
C9
RXSQLCH
I
LVTTL
Receiver Data Squelch.
When this input is low the data on RXD-
OUT[15:0] is forced to a zero state. Set
RXSQLCH high for normal operation.
The RXSQLCH input is ignored when operating
in diagnostic loopback mode (DLBK = 0).
Note: This input has an internal pullup.
C4
SLICELVL
I
Slicing Level Adjustment.
Applying an analog voltage to this pin allows
adjustment of the slicing level applied to the
input data eye. Tying this input to VREF sets the
slicing offset to 0.
E12
SLICEMODE
I
LVTTL
Slice Level Adjustment Mode.
The SLICEMODE input is used to select the
mode of operation for slicing level adjustment.
When SLICEMODE = 0, absolute slice mode is
selected. When SLICEMODE = 1, proportional
slice mode is selected.
Note: This input has an internal pulldown.
N2
N1
TXCLK16IN+
TXCLK16IN–
ILVDS
Differential Transmit Data Clock Input.
The rising edge of this input clocks data present
on TXDIN into the device. TXCLK 16IN is also
used as the Si5100 reference clock when the
REFSEL input is set low.
Pin Number(s)
Name
I/O
Signal Level
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72V3650L7-5BB | IC FIFO SS 2048X36 7-5NS 144BGA |
| MS27513E22F21PB | CONN RCPT 21POS BOX MNT W/PINS |
| MS27472T10F13PA | CONN RCPT 13POS WALL MT W/PINS |
| VI-25B-IW-F4 | CONVERTER MOD DC/DC 95V 100W |
| VE-21J-MX-F2 | CONVERTER MOD DC/DC 36V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI-51010-F | 制造商:Bel Fuse 功能描述:- Trays |
| SI-51011-F | 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:SI-51011-F |
| SI-51012-F | 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:SI-51012-F |
| SI-51013-F | 制造商:Bel Fuse 功能描述:- Bulk |
| SI-51014-F | 功能描述:CONN MAGJACK 1PT GIGABIT SHLD RoHS:是 類別:連接器，互連式 >> 模塊 - 帶磁性元件的插座 系列:MagJack® ST SI-50000 標(biāo)準(zhǔn)包裝:63 系列:Mag45 連接器類型:RJ45 端口數(shù):1 行數(shù):1 安裝類型:面板安裝，通孔，直角 速度:10/100 Base-T 板上方高度:0.555"（14.10mm） LED 顏色:綠 - 綠 每一插座芯體的數(shù)目:5 屏蔽:屏蔽 翼片方向:上 特點(diǎn):板鎖 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。