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參數(shù)資料
| 型號(hào)： | SI5013-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 28MLP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 675MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-MLP-EP（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1277 |
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Si5013
Rev. 1.6
15
4.11.2. Jitter Transfer
The
Si5013
exceeds
all
relevant
Bellcore/ITU
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency.
These measurements are made with an input test signal
that is degraded with sinusoidal jitter whose magnitude
is defined by the mask in Figure 9.
Figure 9. Jitter Transfer Specification
4.11.3. Jitter Generation
The Si5013 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5013 typically generates less than 3.0 mUIrms of jitter
when presented with jitter-free input data.
4.12. RESET/DSPLL Calibration
The Si5013 achieves optimal jitter performance by
automatically calibrating the loop gain parameters within
the DSPLL on powerup. Calibration may also be
initiated by a high-to-low transition on the RESET/CAL
pin. The RESET/CAL pin must be held high for at least
1 s. When RESET/CAL is released (set to low) the
digital
logic
resets
to
a
known
initial
condition,
recalibrates the DSPLL, and begins to lock to the
incoming data stream. For a valid reset to occur when
using Reference mode, a proper, external reference
clock frequency must be applied.
4.13. Clock Disable
The Si5013 provides a clock disable pin (CLK_DSBL)
that is used to disable the recovered clock output
(CLKOUT). When the CLK_DSBL pin is asserted, the
positive and negative terminals of CLKOUT are tied to
VDD through 100
Ω on-chip resistors.
4.14. Data Squelch
The Si5013 provides a data squelching pin (DSQLCH)
that is used to set the recovered data output (DOUT) to
binary zero. When the DSQLCH pin is asserted, the
DOUT+ signal is held low and the DOUT– signal is held
high. This pin can be is used to squelch corrupt data
during LOS and LOL situations. Care must be taken
when ac coupling these outputs; a long string of zeros
or ones will not be held through ac coupling capacitors.
4.15. Device Grounding
The Si5013 uses the GND pad on the bottom of the 28-
pin micro leaded package (QFN) for device ground. This
pad should be connected directly to the analog supply
ground. See Figure 15 on page 19 and Figure 16 on
page 23 for the ground (GND) pad location.
4.16. Bias Generation Circuitry
The Si5013 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces
power
consumption
versus
traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 k
Ω (1%) resistor
connected between REXT and GND.
4.17. Voltage Regulator
The Si5013 operates from a 3.3 V external supply
voltage. Internally the device operates from a 2.5 V
supply. The Si5013 regulates 2.5 V internally down from
the external 3.3 V supply.
In addition to supporting 3.3 V systems, the on-chip
linear regulator offers better power supply noise
rejection versus a direct 2.5 V supply.
4.18. Differential Input Circuitry
The Si5013 provides differential inputs for both the high-
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown
in
Figures
and
11,
respectively.
In
applications where direct dc coupling is possible, the
0.1 F capacitors may be omitted. (LOS operation is
only guaranteed when ac coupled.) The data input
limiting amplifier requires an input signal with a
differential peak-to-peak voltage as specified in Table 2
REFCLK
input
differential
peak-to-peak
voltage
requirement is also specified in Table 2.
0.1 dB
Jitter
Transfer
Fc
Frequency
20 dB/Decade
Slope
Fc
(kHz)
SONET
Data Rate
OC-12
OC-3
500
130
Acceptable
Range
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5013-D-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 OC-3/12 STM-1/4 Sonet/SDH CDR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5013-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 SNT/SDH OC3/12 STM1/ w/limit amp 3.3V RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
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