參數(shù)資料
型號(hào): SI5010-B-GM
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK/DATA RECOVERY LP 20-QFN
標(biāo)準(zhǔn)包裝: 75
系列: DSPLL®
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR)
PLL:
主要目的: SONET/SDH,ATM 應(yīng)用
輸入: 時(shí)鐘
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 666MHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 628 (CN2011-ZH PDF)
其它名稱: 336-1743-5
Si5010
14
Rev. 1.4
5. Pin Descriptions: Si5010
Figure 10. Si5010 Pin Configuration
Table 8. Si5010 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1
REXT
External Bias Resistor.
This resistor is used by onboard circuitry to estab-
lish bias currents within the device. This pin must
be connected to GND through a 10 k
Ω (1%) resis-
tor.
2, 7, 11, 14
VDD
2.5 V
Supply Voltage.
Nominally 2.5 V.
3, 8, 18, and
GND Pad
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 20-pin micro leaded package (see Figure 11)
must be connected directly to supply ground.
4
5
REFCLK+
REFCLK–
ISee Table 2
Differential Reference Clock.
The reference clock sets the initial operating fre-
quency used by the onboard PLL for clock and data
recovery. Additionally, the reference clock is used to
derive the clock output when no data is present.
6LOL
O
LVTTL
Loss-of-Lock.
This output is driven high when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 7.
9
10
DIN+
DIN–
ISee Table 2
Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins.
GND
Pad
Connection
15
14
13
12
11
PWRDN/CAL
DOUT+
VDD
DOUT–
VDD
1
2
3
4
5
VDD
GND
REFCLK–
REXT
REFCLK+
20
19
18
17
16
NC
RAT
ESEL
CL
KO
UT
CL
KO
UT
+
GND
6
7
8
9
10
LOL
GND
DIN+
DIN–
VDD
Top View
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SI5010-GM 制造商:SILABS 制造商全稱:SILABS 功能描述:OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC