參數(shù)資料
型號(hào)： SI3225-G-GQ
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 77/112頁(yè)
文件大小： 0K
描述： IC PROSLIC/CODEC DUAL 64TQFP
標(biāo)準(zhǔn)包裝： 160
系列： ProSLIC®
功能： 用戶線路接口概念（SLIC），CODEC
接口： GCI，PCM，SPI
電路數(shù)： 2
電源電壓： 3.3V，5V
電流 - 電源： 65mA
功率（瓦特）： 941mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤
包括： 電池切換，BORSCHT 功能，DTMF 生成和解碼，F(xiàn)SK 音調(diào)生成，調(diào)制解調(diào)器和傳真音調(diào)檢測(cè)
Si3220/25 Si3200/02
Rev. 1.3
67
Not
Recommended
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3.20.4. Tone Generator Interrupts
Both the active and inactive timers can generate an
interrupt to signal “on/off” transitions to the software.
The timer interrupts for tone generator 1 can be
individually enabled by setting the OS1TAE and
OS1TIE bits. Timer interrupts for tone generator 2 are
OS2TAE and OS2TIE. A pending interrupt for each of
the timers is determined by reading the OS1TAS,
OS1TIS, OS2TAS, and OS2TIS bits in the IRQVEC1
register.
3.21. Caller ID Generation
The Dual ProSLIC devices generate caller ID signals in
compliance with various Bellcore and ITU specifications
as described in Table 36 by providing continuous phase
binary
frequency
shift
keying
(FSK)
modulation.
Oscillator 1 is required because it preserves phase
continuity during frequency shifts whereas Oscillator 2
does not. Figure 37 illustrates a typical caller ID
transmission sequence in accordance with Bellcore
requirements.
The register and RAM locations for caller ID generation
are listed in Table 37. Caller ID data is entered into the
8-bit FSKDAT register. The data byte is double buffered
so that the Dual ProSLIC can generate an interrupt
indicating the next data byte can be written when
processing begins on the current data byte. The caller
ID data can be transmitted in one of two modes
controlled
by
the
O1FSK8
register
bit.
When
O1FSK8 = 0 (default case), the 8-bit caller ID data is
transmitted with a start bit and stop bit to create a 10-bit
data sequence. If O1FSK8 = 1, the caller ID data is
transmitted as a raw 8-bit sequence with no start or stop
bits. The value programmed into the OSC1TA register
determines the bit rate, and the interrupt rate is equal to
the bit rate divided by the data sequence length (8 or 10
bits).
Table 36. FSK Modulation Requirements
Parameter
ITU-T V.23 Bellcore GR-30-CORE
Mark Frequency (logic 1)
1300 Hz
1200 Hz
Space Frequency (logic 0)
2100 Hz
2200 Hz
Transmission Rate
1200 baud
Table 37. Register and RAM Locations used for Caller ID Generation
Parameter
Register/RAM
Mnemonic
Register/RAM Bits
Description/Range (LSB Size)
FSK Start & Stop Bit Enable
OMODE
O1FSK8
Enable/disable
Oscillator 1 Active Timer
O1TALO/
O1TAHI
OSC1TA[15:0]
0 to 2.73 s (41.66 s)*
FSK Data Byte
FSKDAT
FSKDAT[7:0]
Caller ID data
FSK Frequency for Space
FSKFREQ0
FSKFREQ0[15:3]
Audio range
FSK Frequency for Mark
FSKFREQ1
FSKFREQ1[15:3]
Audio range
FSK Amplitude for Space
FSKAMP0
FSKAMP0[15:3]
FSK Amplitude for Mark
FSKAMP1
FSKAMP1[15:3]
FSK 0-1 Transition Freq, High
FSK01HI
FSK01HI[15:3]
FSK 0-1 Transition Freq, Low
FSK01LO
FSK01LO[15:3]
FSK 1-0 Transition Freq, High
FSK10HI
FSK10HI[15:3]
FSK 1-0 Transition Freq, Low
FSK10LO
FSK10LO[15:3]
*Note: Oscillator 1 active timer range and LSB stage valid only for FSK mode.
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