參數(shù)資料
型號(hào)： SI3068-B-FS
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 6/40頁(yè)
文件大?。?/td> 0K
描述： IC FCC+ EMBEDDED DAA 8SOIC
標(biāo)準(zhǔn)包裝： 96
功能： 直接存取裝置（DAA）
電路數(shù)： 1
電流 - 電源： *
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm Width）裸露焊盤
供應(yīng)商設(shè)備封裝： 8-SOIC-EP
包裝： 管件
包括： 結(jié)帳音調(diào)檢測(cè)，線路電壓監(jiān)視器，回路電流監(jiān)視器，過(guò)載檢測(cè)，振鈴檢測(cè)器
Si3068
14
Rev. 1.0
4.8. Transhybrid Balance
The Si3068 contains an on-chip analog hybrid that
performs the 2- to 4-wire conversion and near-end echo
cancellation.
4.9. Ring Detection
Ring detection can be performed by monitoring the ring
detector output or by observing the audio CODEC data.
The ring detector output can be monitored with the
register bits, RDTN, RDTP, and RDT (Register 5, bits 6,
5, and 2). Software must detect the frequency of the ring
signal to distinguish a ring from pulse dialing by
telephone equipment connected in parallel.
Alternatively, hardware ring validation can be used. See
The ring detector output is controlled by the RFWE bit
(Register 18, bit 1). When the RFWE bit is 0 (default
mode), only positive ring signals are reported by the ring
detector. A positive ring signal is defined as a voltage
greater than the ring threshold at the QE pin.
Conversely, a negative ring signal is defined as a
voltage less than the negative ring threshold. When the
RFWE bit is 1, the ring detector reports both positive
and negative ring signals.
The RDTP and RDTN behavior is based on the ring
voltage. When the signal is above the positive ring
threshold, the RDTP bit is set. When the signal is below
the negative ring threshold, the RDTN bit is set. When
the signal is between these thresholds, neither bit is set.
The RDT behavior is also based on the ring voltage.
When the RFWE bit is 0, a positive ring signal sets the
RDT bit for a period of time. When the RFWE bit is 1,
either a positive or negative ring signal sets the RDT bit.
The audio CODEC data also signals ring events when
on-hook. If the RFWE bit is 0, the CODEC output is
fixed at –32768 when a ring is not present. The CODEC
data becomes +32767 upon detection of a positive ring.
Negative rings will be ignored and have no effect on the
CODEC data while RFWE is 0.
When on-hook with RFWE = 1, the CODEC data is
fixed at +1228 when a ring is not present. The CODEC
data becomes +32767 upon detection of a positive ring
or –32768 upon detection of a negative ring.
The RDT bit acts like a one shot. When a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected before the one shot counter
reaches 0 (5 seconds), the RDT bit returns to 0. The
RDT bit is also reset to 0 by an off-hook event.
4.10. Ring Validation
This feature prevents false ring detection by validating
the ring parameters. Invalid signals, such as line-
voltage changes when a parallel handset goes off-hook,
pulse dialing, polarity reversals, and high-voltage line
tests, are ignored. Ring validation can be enabled
during normal operation and in low-power sleep mode.
The ring validation circuit operates by calculating the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High- and low-frequency
tolerances are programmable in the RAS[5:0] and
RMX[5:0] fields. The RCC[2:0] bits define the length of
time the ring signal must be within tolerance. Once the
duration of the ring frequency is validated by the RCC
bits, the circuitry stops checking for frequency tolerance
and begins checking for the end of the ring signal, which
is defined by a lack of additional threshold crossings for
a period of time configured by the RTO[3:0] bits. When
the ring frequency is first validated, a timer defined by
the RDLY[2:0] bits is started. If the RDLY[2:0] timer
expires before the ring timeout, the ring is validated, and
a valid ring is indicated. If the ring timeout expires
before the RDLY[2:0] timer, a valid ring is not indicated.
Ring validation requires five parameters:
Timeout parameter to place a lower limit on the
frequency of the ring signal on the RAS[5:0] bits
(Register 24, bits 5:0). The frequency is measured
by calculating the time between crossings of positive
and negative ring thresholds.
Minimum count to place an upper limit on the
frequency on the RMX[5:0] bits (Register 22, bits
[5:0]).
Time interval over which the ring signal must be the
correct frequency on the RCC[2:0] bits (Register 23,
bits [2:0]).
Timeout period that defines when the ring pulse has
ended with the most recent ring threshold crossing
on the RTO [3:0] bits (Register 23, bits 6:3).
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
help accommodate distinctive ring on the RDLY [2]
bit (Register 23, bit 7).
The ring validation enable bit, RNGV (Register 24, bit
7), enables or disables the ring validation feature in
normal operating mode and low-power sleep mode. For
further details, see “AN72: Ring Detection/Validation
with the Si305x DAAs.”
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