參數(shù)資料
型號(hào)： SI3000-C-GS
廠商： Silicon Laboratories Inc
文件頁數(shù)： 9/34頁
文件大?。?/td> 0K
描述： IC VOICE CODEC 3.3V/5V 16SOIC
標(biāo)準(zhǔn)包裝： 48
類型： 語音頻帶編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 16 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 無
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 84 / 84
電壓 - 電源，模擬： 3 V ~ 5.25 V
電壓 - 電源，數(shù)字： 3 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
其它名稱： 336-2136-5
Si3000
Rev. 1.4
17
Figure 18. Clock Generation Subsystem (PLL)
2.9. Clock Generation Subsystem
The Si3000 contains an on-chip clock generator. Using
a single MCLK input frequency, the Si3000 can
generate all the desired standard modem sample rates,
as well as the common 11.025 kHz rate for audio
playback.
The clock generator consists of a phase-locked loop
(PLL1) that achieves the desired sample frequency.
illustrates
the
clock
generator.
The
architecture of the PLL allows for fast lock time on initial
start-up, fast lock time when changing modem sample
rates and high noise immunity. A large number of MCLK
frequencies between 1 MHz and 60 MHz are supported.
2.9.1. Programming the Clock Generator
As noted in Figure 18, the clock generator must output a
clock equal to 1024*Fs, where Fs is the desired sample
rate. The 1024*Fs clock is determined through
programming of the following registers:
Register 3 - N1 divider, 8 bits.
Register 4 - M1 divider, 8 bits
N1 (register 3) and M1 (register 4) are 8-bit unsigned
values. FMCLK is the clock provided to the MCLK pin.
Table 12 lists several standard crystal rates that could
be supplied to MCLK.
When programming the registers of the clock generator,
the order of register writes is important. For PLL
updates, N1 (register 3) must always be written first,
immediately followed by a write to M1 (register 4).
Note:
The values shown in Table 12 satisfy the equations
above. However, when programming the registers for
N1 and M1, the value placed in these registers must be
one less than the value calculated from the equations.
÷ N1
FUP1
MCLK
VCO1
P
D
÷ M1
8 bits
÷ 5 or
÷ 10*
1024Fs
FPLL1
*Note: See PLL bit in Register 2.
Table 12. MCLK Examples for 8 kHz
MCLK (MHz)
N1
M1
1.8432
9
200
4.0000
25
256
4.0960
1
10
5.2800
33
256
5.7600
9
64
6.1440
3
20
8.1920
1
5
9.2160
9
40
10.0800
63
256
10.5600
33
128
11.0592
27
100
12.288
3
10
14.7456
9
25
16.0000
25
64
18.4320
9
20
24.5760
3
5
25.8048
63
100
33.7600
211
256
44.2368
27
25
46.0800
9
8
47.9232
117
100
48.0000
75
64
56.0000
175
128
59.200
185
128
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