參數(shù)資料
型號: SDM-09060-B1F
英文描述: 925-960 MHz Class AB 65W Power Amplifier Module
中文描述: 925-960兆赫65瓦AB類功率放大器模塊
文件頁數(shù): 2/5頁
文件大小: 230K
代理商: SDM-09060-B1F
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-104211 Rev D
SDM-09060-B1F 925-960 MHz 65W Power Amp Module
Pin Description
Pin #
Function
Description
1
V
GS1
Ground
LDMOS FET Q1 gate bias. V
GSTH
3.0 to 5.0 VDC. See Notes 2, 3 and 4
Module Topside ground.
2,4,7,9
3
RF Input
Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
5
V
GS2
V
D2
LDMOS FET Q2 gate bias. V
GSTH
3.0 to 5.0 VDC. See Notes 2, 3 and 4
LDMOS FET Q2 drain bias. See Note 1.
6
8
RF Output
Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
10
V
D1
LDMOS FET Q1 drain bias. See Note 1.
Flange
Ground
Baseplate provides electrical ground and a thermal transfer path for the device. Proper mounting assures
optimal performance and the highest reliability. See Sirenza applications note AN-054 Detailed Installation Instructions for
Power Modules.
Simplified Device Schematic
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
Note 1:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the V
D
leads to
accommodate modulated signals.
Note 2:
Gate voltage must be applied to V
GS
leads simultaneously with
or after application of drain voltage to prevent potentially
destructive oscillations. Bias voltages should never be applied
to a module unless it is properly terminated on both input and
output.
Note 3:
The required V
GS
corresponding to a specific I
DQ
will vary from
module to module and may differ between V
GS1
and V
GS2
on
the same module by as much as ±0.10 volts due to the normal
die-to-die variation in threshold voltage for LDMOS transistors.
Note 4:
The threshold voltage (V
GSTH
) of LDMOS transistors varies with
device temperature. External temperature compensation may
be required. See Sirenza application notes AN-067 LDMOS
Bias Temperature Compensation.
Note 5:
This module was designed to have it's leads hand
soldered to an adjacent PCB. The maximum soldering iron tip
temperature should not exceed 700° C, and the soldering iron
tip should not be in direct contact with the lead for longer than
10 seconds. Refer to app note AN054 (www.sirenza.com) for
further installation instructions.
Absolute Maximum Ratings
Parameters
Value
Unit
Drain Voltage (V
DD
)
RF Input Power
35
V
+37
dBm
Load Impedance for Continuous Operation Without
Damage
5:1
VSWR
Control (Gate) Voltage, VDD = 0 VDC
15
V
Output Device Channel Temperature
+200
oC
Operating Temperature Range
-20 to
+90
oC
Storage Temperature Range
-40 to
+100
oC
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
10
9
8
7
6
5
4
3
2
1
Case Flange = Ground
Q2
Q1
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