參數(shù)資料
型號: SDA9401
廠商: Electronic Theatre Controls, Inc.
英文描述: Scan Rate Converter using Embedded DRAM Technology Units
中文描述: 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股
文件頁數(shù): 56/69頁
文件大?。?/td> 1142K
代理商: SDA9401
Micronas
56
Preliminary Data Sheet
SDA 9401
D3
FLASHON
Flash of output picture:
1: on
0: off
Chrominance output format:
1: 2’s complement input (-128...127)
0: unsigned input (0...255)
inside the SDA 9401 the data are always processed as unsigned data
should be set to 00
D2
TWOOUT
D1...D0
Subaddress 18
Bit
Name
Function
D7...D4
UBORDER
U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0 0 0 =
10000000 = 128), UBORDER defines the 4 MSB’s of a 8 bit value
V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0 0 0 =
10000000 = 128), VBORDER defines the 4 MSB’s of a 8 bit value
D3...D0
VBORDER
Subaddress 19
Bit
Name
Function
D7...D4
PLL2RA
PLL2 range, only for test purposes [PPL2RA=0]
D3
CLK21EN
PLL2 input signal (see also
Clock concept
on page 27):
1: external CLK1
0: external X1/CLK2
Internal clock switch for CLKOUT (see also
Clock concept
on page 27):
1: PLL2 output
0: external CLK1
should be set to 00
D2
CLK11EN
D1...D0
Subaddress 1A
Bit
Name
Function
D7...D0
VPAN
Vertical adjustment of the output picture [VPAN = 0]
Subaddress 17
Bit
Name
Function
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