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SDA 525x
Semiconductor Group
5
1998-04-08
1
The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acquisition
hardware modul, a display generator for “Level 1” TTX data and an 8 bit microcontroller
running at 333 ns cycle time. The controller with dedicated hardware guarantees
flexibility, does most of the internal processing of TTX acquisition, transfers data to/from
the external memory interface and receives/transmits data via
interfaces. The block diagram shows the internal organization of the SDA 525x. The
Slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kbyte. The
microcontroller firmware does the total acquisition task (hamming- and parity-checks,
page search and evaluation of header control bits) once per field.
General Description
I
2
C and UART user
2
Features
Acquisition
Feature selection via special function register
Simultaneous reception of TTX, VPS and WSS
Fixed framing code for VPS and TTX
Acquisition during VBI
Direct access to VBI RAM buffer
Acquisition of packets X/26, X/27, 8/30 (firmware)
Assistance of all relevant checks (firmware)
1-bit framing code error tolerance (switchable)
Display
Features selectable via special function register
50/60 Hz display
Level 1 serial attribute display pages
Blanking and contrast reduction output
8 direct addressable display pages for SDA 5250, SDA 5254 and SDA 5255
1 direct addressable display page for SDA 5251 and SDA 5252
12
×
10 character matrix
96 character ROM (standard G0 character set)
143 national option characters for 11 languages
288 characters for X/26 display
64 block mosaic graphic characters
32 characters for OSD in expanded character ROM + 32 characters inside OSD box
Conceal/reveal
Transparent foreground/background - inside/outside of a box
Contrast reduction inside/outside of a box
Cursor (colour changes from foreground to background colour)
Flash (flash rate 1s)