參數(shù)資料
型號(hào): SDA5250-2
廠商: SIEMENS A G
元件分類: 圖文
英文描述: ICs for Consumer Electronics
中文描述: TELETEXT DECODER, PQCC84
文件頁數(shù): 106/143頁
文件大小: 1050K
代理商: SDA5250-2
SDA 525x
Semiconductor Group
106
1998-04-08
6.3.11
The on-chip-PWM unit consists of 6 quasi-8-Bit and 2 quasi-14-Bit PWM channels.
Controlled via special function registers, each channel can be enabled individually.
The base frequency of an 8-Bit channel is derived from the overflow of a 6-Bit counter
which counts internal clocks. On every counter overflow, the enabled PWM lines will be
set to one (exception: compare values are zero) and will be reset when the 6 MSBs of
the PWCOMPx-register match the counter value. To get an overall resolution of 8 bit, the
high-time is stretched periodically, depending on the 2 LSBs of the PWCOMPx-register.
For example, if PWCOMPx[1:0] is ‘10’, the high-time will be stretched in every second
base cycle.
This type of PWM channel is called “6 plus 2”.
Pulse Width Modulation Unit (PWM)
Figure 36
Simplified Example with PWCOMPx[1:0]= ‘10’
The function of an 14-Bit channel is very similar. Here, an 8-Bit counter gives the base
frequency. All 8 bits of the PWCOMPx registers are compared with the counter value,
and the value in PWEXTx register gives the number of stretchings within 64 successive
base cycles. Thus, this type of PWM channel is called “8 plus 6”. The
the influence of the PWEXTx register bits on cycles to be stretched.
Table 24
shows
Table 23
Effect of PWCOMPx-Bits for 8-Bit PWM
PWCOMPx
Cycle Number ‘Stretched’
Bit 1
Bit 0
2
1,3
‘stretched’
Cycle 1
Cycle 2
Cycle 3
Cycle 0
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