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參數(shù)資料
| 型號： | SDA3302-5X6 |
| 廠商： | SIEMENS A G |
| 元件分類： | XO, clock |
| 英文描述： | GHz PLL with I2C Bus and Four Chip Addresses |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 864K |
| 代理商： | SDA3302-5X6 |
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Semiconductor Group
16
Characteristics
V
S
= 5 V;
T
A
= 25
°
C
Parameter
Symbol
2)
Limit Values
Unit
Test Condition
Test
Circuit
min.
typ.
max.
Current
consumption
I
S
35
mA
V
S
= 5 V
1
Crystal-oscillator
frequency
f
2, 3
3.99975 4.000 4.00025 MHz
series capaci-
tance 18 pF;
f
xtal
= 4 MHz
1
Oscillator level
1)
(Voltage across
crystal)
V
2, 3
2.6
Vpp
Margin from 1st
1)
and 2nd harmonic
20
dB
Input Sensitivity UHF/VHF
a
15
a
15
a
15
– 27/10
– 27/10
– 27/10
3/315
3/315
3/315
3)
f
15
= 70-500 MHz
f
15
= 1000 MHz
f
15
= 1100 MHz
2
2
2
Band-Select Outputs P0-P2
(switch with open collector)
Reserve current
I
13H
10
μ
A
V
13H
= 13.5 V
3
Residual voltage
V
13L
0.5
V
I
13H
= 20 mA
3
Port Outputs P4-P7
(switch with open collector)
Reserve current
I
9H
10
μ
A
V
9H
= 13.5 V
4
Residual voltage
V
9L
0.5
V
I
9L
= 1.7 mA
4
Note: The sum of the currents in ports P0-P7 must not exceed 25 mA
Phase-Detector Output PD
Pump current
I
1H
±
90
±
230
±
300
μ
A
5
I
= HIGH;
V
1
= 2 V
Pump current
I
1H
±
22
±
50
±
75
μ
A
5
I
= LOW;
V
1
= 2 V
Output voltage
V
1L
1.0
2.5
V
locked
1) Design note: no 100 % final inspection.
2) Pin nos. refer to P-DIP-18 package
3) dBm/mV
rms
into 50
SDA 3302 Family
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