參數(shù)資料
型號： SCH-V
廠商： Sharp Corporation
英文描述： 8 M-bit (1 MB x 8) Smart 5
中文描述： 8 M位（1字節(jié)× 8）智能5
文件頁數(shù)： 16/40頁
文件大?。?/td> 266K
代理商： SCH-V
LH28F008SC-V/SCH-V
- 16 -
MASTER
LOCK-BIT LOCK-BIT
BLOCK
OPERATION
RP#
EFFECT
Block Erase
or Byte Write
0
V
IH
or V
HH
Block Erase and Byte Write Enabled
V
IH
Block is Locked. Block Erase and Byte Write Disabled
V
HH
Block Lock-Bit Override. Block Erase and Byte Write Enabled
V
IH
or V
HH
Set Block Lock-Bit Enabled
V
IH
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
V
HH
Master Lock-Bit Override. Set Block Lock-Bit Enabled
V
IH
Set Master Lock-Bit Disabled
V
HH
Set Master Lock-Bit Enabled
V
IH
or V
HH
Clear Block Lock-Bits Enabled
V
IH
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled
V
HH
Master Lock-Bit Override. Clear Block Lock-Bits Enabled
X
1
Set Block
Lock-Bit
0
X
1
X
Set Master
Lock-Bit
X
X
Clear Block
Lock-Bits
0
X
1
X
Table 5 Write Protection Alternatives
Table 6 Status Register Definition
ECLBS
BWSLBS
5
4
WSMS
7
ESS
6
VPPS
3
BWSS
2
DPS
1
R
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 =
ERASE AND CLEAR LOCK-BITS STATUS (ECLBS)
1 = Error in Block Erase or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4 =
BYTE WRITE AND SET LOCK-BIT STATUS (BWSLBS)
1 = Error in Byte Write or Set Master/Block Lock-Bit
0 =
Successful Byte Write or Set Master/Block Lock-Bit
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
SR.2 = BYTE WRITE SUSPEND STATUS (BWSS)
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock
Detected, Operation Abort
0 = Unlock
SR.0 =
RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES :
Check RY/BY# or SR.7 to determine block erase, byte write,
or lock-bit configuration completion.
SR.6-0 are invalid while SR.7 = "0".
If both SR.5 and SR.4 are "1"s after a block erase or lock-bit
configuration attempt, an improper command sequence was
entered.
SR.3 does not provide a continuous indication of V
PP
level.
The WSM interrogates and indicates the V
PP
level only after
Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear
Block Lock-Bits command sequences.
SR.3 is not guaranteed to reports accurate feedback only
when V
PP
≠
V
PPH1/2
.
SR.1 does not provide a continuous indication of master and
block lock-bit values. The WSM interrogates the master lock-
bit, block lock-bit, and RP# only after Block Erase, Byte Write,
or Lock-Bit configuration command sequences. It informs the
system, depending on the attempted operation, if the block
lock-bit is set, master lock-bit is set, and/or RP# is not V
HH
.
Reading the block lock and master lock configuration codes
after writing the Read Identifier Codes command indicates
master and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
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