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參數(shù)資料
| 型號： | SCG4500-155.52M |
| 廠商： | Connor-Winfield |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC CLK GEN 155.52MHZ OUT SMD |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 155.52MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 18-SMD 模塊 |
| 包裝： | 管件 |
| 其它名稱： | CW641 SCG4500 155.52M SCG4500155.52M |
Preliminary Data Sheet #: SG026
Page 2 of 16
Rev: P08
Date: 10/08/02
Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
General Description
The SCG4500 Series is a mixed-signal phase locked
loop generating LVPECL outputs from an intrinsically
low jitter, voltage controlled, crystal oscillator. The
LVPECL outputs may be disabled.
The SCG4500 Series can lock to one of two external
references, which is selectable using the SEL
AB input
select pin. The unit has a fast acquisition time of about
1.5 seconds and it is tolerant of different reference duty
cycles.
The SCG4500 Series includes an alarm output that
indicates deviations from normal operation. If a Loss-
of-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FR
status
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to ±20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1” x 1.025” x .45” on a
6 layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Maximum Dimension Package Outline
Figure 1
Model Comparison Table
Table 1
Dual
Max
LVPECL
Model
Input
Duty
Oscillator Output
Notes
Ref Freq
Cycle
(Pins 16 & 18)
SCG4500
8 kHz/8 kHz
40/60
77.76 MHz,155.52 MHz,125 MHz
Basic Model
SCG4510
1.544MHz/1.544MHz
40/60
155.52 MHz
SCG4520
19.44 MHz/19.44 MHz
40/60
77.76 MHz,155.52 MHz
*Features which differentiate a model from the base model (SCG4500) are highlighted in boldface color and in the notes column.
Block Diagram
Figure 2
8 KHz PHASE
ALIGNER
REFB
REFA
SEL AB
ANALOG
FILTER
Q
QN
1 / N
ALARM
LOW JITTER
VCXO
FREE RUN STATUS
OPTIONAL
REFERENCE
OUTPUT
FORCE
FREE RUN
ENABLE/
TRI-STATE
33
10 k
10 k
10 k
10 k
33
33
DPFD
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SCG4501 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Clock Generators |
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| SCG4520 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Clock Generators |
| SCG4521 | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:Synchronous Clock Generators |
| SCG4540 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Clock Generators |
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