參數(shù)資料
型號(hào): SCAN18374T
廠商: Fairchild Semiconductor Corporation
英文描述: D-Type Flip-Flop with 3-STATE Outputs
中文描述: D類觸發(fā)器觸發(fā)器3態(tài)輸出
文件頁(yè)數(shù): 9/12頁(yè)
文件大?。?/td> 99K
代理商: SCAN18374T
9
www.fairchildsemi.com
S
AC Electrical Characteristics
Scan Test Operation
Note 10:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note:
All Propagation Delays involving TCK are measured from the falling edge of TCK.
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
Typ
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Min
3.5
Units
(V)
(Note 10)
5.0
Min
3.5
Max
13.2
Max
14.5
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
PLH
,
t
PHL
Propagation Delay
ns
TCK to TDO
Disable Time
TCK to TDO
3.5
2.5
2.5
13.2
11.5
11.5
3.5
2.5
2.5
14.5
11.9
11.9
5.0
ns
Enable Time
TCK to TDO
Propagation Delay
5.0
3.0
3.0
5.0
14.5
14.5
18.0
3.0
3.0
5.0
15.8
15.8
19.8
ns
5.0
ns
TCK to Data Out
During Update-DR State
Propagation Delay
5.0
18.0
5.0
19.8
t
PLH
,
t
PHL
5.0
5.0
18.6
5.0
20.2
ns
TCK to Data Out
During Update-IR State
Propagation Delay
5.0
18.6
5.0
20.2
t
PLH
,
t
PHL
5.0
5.5
19.9
5.5
21.5
ns
TCK to Data Out
During Test Logic Reset State
Propagation Delay
5.5
19.9
5.5
21.5
t
PLZ
,
t
PHZ
5.0
4.0
16.4
4.0
18.2
ns
TCK to Data Out
During Update-DR State
Propagation Delay
4.0
16.4
4.0
18.2
t
PLZ
,
t
PHZ
5.0
5.0
19.5
5.0
20.8
ns
TCK to Data Out
During Update-IR State
Propagation Delay
5.0
19.5
5.0
20.8
t
PLZ
,
t
PHZ
5.0
5.0
19.9
5.0
21.5
ns
TCK to Data Out
During Test Logic Reset State
5.0
19.9
5.0
21.5
t
PZL
,
t
PZH
Propagation Delay
TCK to Data Out
During Update-DR State
5.0
5.0
5.0
18.9
18.9
5.0
5.0
20.9
20.9
ns
t
PZL
,
t
PZH
Propagation Delay
TCK to Data Out
During Update-IR State
5.0
6.5
6.5
22.4
22.4
6.5
6.5
24.2
24.2
ns
t
PZL
,
t
PZH
Propagation Delay
TCK to Data Out
During Test Logic Reset State
5.0
7.0
7.0
23.8
23.8
7.0
7.0
25.7
25.7
ns
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