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| 型號： | SC486EVB |
| 廠商： | Semtech Corporation |
| 英文描述： | Complete DDR1/2/3 Memory Power Supply |
| 中文描述： | 完全DDR1/2/3內(nèi)存供電 |
| 文件頁數(shù)： | 16/26頁 |
| 文件大?。?/td> | 382K |
| 代理商： | SC486EVB |
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16
2006 Semtech Corp.
www.semtech.com
SC486
POWER MANAGEMENT
Design Procedure (Cont.)
For our DDR2 VDDQ example:
I
RIPPLE_VBAT(MIN)
= 2.62A
P-P
and I
RIPPLE_VBAT(MAX)
= 3.28A
P-P
From this we can calculate the minimum inductor
current rating for normal operation:
)
MIN
(
)
MAX
(
VBAT
2
_
RIPPLE
I
)
MAX
(
OUT
I
)
MIN
(
INDUCTOR
I
A
+
=
For our DDR2 VDDQ example:
I
INDUCTOR(MIN)
= 11.6A
(MIN)
Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R
ESR_ST(MAX)
) and transient ESR
(R
ESR_TR(MAX)
):
(
)
Ohms
I
2
ERR
ERR
R
)
MAX
(
VBAT
_
RIPPLE
DC
ST
)
MAX
(
ST
_
ESR
=
Where ERR
is the static output tolerance and ERR
is
the DC error. The DC error will be 1% plus the tolerance
of the feedback resistors, thus 2% total for 1%
feedback resistors.
For our DDR2 VDDQ example:
ERR
ST
= 72mV and ERR
DC
= 36mV, therefore
R
ESR_ST(MAX)
= 22m
(
)
Ohms
2
I
I
ERR
ERR
R
)
MAX
(
VBAT
_
RIPPLE
OUT
DC
TR
)
MAX
(
TR
_
ESR
+
=
Where ERR
is the transient output tolerance. Note that
this calculation assumes that the worst case load
transient is full load. For half of full load, divide the I
OUT
term by 2.
For our DDR2 VDDQ example:
ERR
TR
= 100mV and ERR
DC
= 36mV, therefore
R
ESR_TR(MAX)
= 5.5m
for a full 10A load transient
We will select a value of 7.5m
maximum for our
design, which would be achieved by using two 15m
output capacitors in parallel.
Note that for constant-on converters there is a minimum
ESR requirement for stability which can be calculated as
follows:
SW
f
OUT
)
MIN
(
ESR
C
2
3
R
π
=
This criteria should be checked once the output
capacitance has been determined.
Now that we know the output ESR we can calculate the
output ripple voltage:
P
P
)
MAX
(
VBAT
_
RIPPLE
I
ESR
)
MAX
(
VBAT
_
RIPPLE
V
V
R
=
and
P
P
)
MIN
(
VBAT
_
RIPPLE
I
ESR
)
MIN
(
VBAT
_
RIPPLE
V
V
R
=
For our DDR2 VDDQ example:
V
RIPPLE_VBAT(MAX)
= 25mV
P-P
and V
RIPPLE_VBAT(MIN)
= 20mV
P-P
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, V
, should be approximately 15mV
at minimum
V
BAT
, and worst case no smaller than 10mV
. If
V
is less than 15mV
the above component
values should be revisited in order to improve this. A small
capacitor, C
, may be required in parallel with the top
feedback resistor, R
, in order to ensure that V
is large
enough. C
should not be greater than 100pF. The value
of C
can be calculated as follows, where R
is the
bottom feedback resistor. Firstly calculating the value of
Z
TOP
required:
(
)
Ohms
015
.
V
015
.
R
Z
)
MIN
(
VBAT
_
RIPPLE
BOT
TOP
=
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