參數(shù)資料
型號(hào)： SC486
廠商： Semtech Corporation
英文描述： Complete DDR1/2/3 Memory Power Supply
中文描述： 完全DDR1/2/3內(nèi)存供電
文件頁(yè)數(shù)： 13/26頁(yè)
文件大?。?/td> 382K
代理商： SC486
13
2006 Semtech Corp.
www.semtech.com
SC486
POWER MANAGEMENT
POR, UVLO and Softstart
An internal power-on reset (POR) occurs when VCCA
exceeds 3V, starting up the internal biasing. VCCA
undervoltage lockout (UVLO) circuitry inhibits the whole
controller until VCCA rises above 4.2V. At this time the
UVLO circuitry enables the REF buffer, resets the fault
latch and soft start timer, and allows switching to occur,
if enabled. Switching always starts with DL to charge up
the BST capacitor. With the softstart circuit
(automatically) enabled, it will progressively limit the
output current (by limiting the current out of the ILIM pin)
over a predetermined time period of 440 switching cycles.
The ramp occurs in four steps:
1) 110 cycles at 25% ILIM with double minimum off-time
(for purposes of the on-time one-shot, there is an
internal positive offset of 120mV to VOUT during this
period to aid in startup)
2) 110 cycles at 50% ILIM with normal minimum off-time
3) 110 cycles at 75% ILIM with normal minimum off-time
4) 110 cycles at 100% ILIM with normal minimum
off-time. At this point the output undervoltage and power
good circuitry is enabled.
When VDDQ reaches 0.5V, the REF output is enabled
and rises to VDDQS/2. VTT attempts to track REF but its
own soft start circuitry will limit its rise rate to 6mV/μs. If
VDDQ is rising slow enough, VTT will rise at 6mV/μs until
it reaches VDDQ/2 and then track VDDQ.
There is 100mV of hysteresis built into the UVLO circuit
and when VCCA
falls to 4.1V (nom.) the output drivers
are shut down and tri-stated.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. An adaptive dead-time circuit monitors the DL
output and prevents the high-side MOSFET from turning
on until DL is fully off (below ~1V). Semtech’s
SmartDriver
FET drive first pulls DH high with a pull-up
resistance of 10
(typ.) until LX = 1.5V (typ.). At this
point, an additional pull-up device is activated, reducing
the resistance to 2
(typ.). This negates the need for an
external gate or boost resistor. The adaptive dead-time
circuit also monitors the phase node, LX, to determine
the state of the high side MOSFET, and prevents the low-
side MOSFET from turning on until DH is fully off (LX
below ~1V). Be sure to have low resistance and low
inductance between the DH and DL outputs to the gate
of each MOSFET.
DDR Reference Buffer
The reference buffer is capable of driving 10mA and
sinking 25μA. Since the output is class A, if additional
sinking is required an external pulldown resistor can be
added. Make sure that the ground side of this pulldown
is tied to VSSA. As with most opamps, a small resistor is
required when driving a capacitive load. To ensure stability
use either a 10
resistor in series with a 1μF capacitor
or a 100
resistor in series with a 0.1μF capacitor from
REF to VSSA.
VTT Sink/Source Output
The VTT regulator is a sink/source LDO capable of
supplying peak currents up to 3.6A. It has been designed
to operate with output capacitances as low as 20μF (two
10μF 1210 ceramic capacitors). These capacitors need
to be placed directly across the VTT and PGND2 pins to
minimize parasitic resistance and inductance. Additional
ceramic capacitors may be used to improve transient
response further if desired. The VTT input requires a 1μF
ceramic capacitor for bypass purposes located right at
the pin. If the output capacitors for the power rail being
used for VTTIN are far from the part then additional bulk
capacitance of two 10μF ceramic capacitors should be
added.
COMP Pin
The VTT COMP pin is provided to permit the addition of a
zero into the VTT control loop by adding a resistor (less
than 100
) between COMP and REF and a capacitor
from COMP to VTTS (R7 and C3 in Figure 2). The zero
frequency should be set to approximately 10 times the
unity gain bandwidth, which is ~1MHz, therefore f
Z
should
be ~10MHz. f
Z
is given by the following equation:
C
R
2
1
f
Z
π
=
Typically this compensation will not be required, so C3
should be no-pop and R7 should be 0
or 10
.
VTTS Pin
The VTTS pin is used to kelvin sense the VTT output. An
RC filter (with R from VTT to VTTS less than 100
and C
from VTTS to VSSA, R8 and C7 in Figure 2) may be used
to compensate any zeroes created by less than optimal
ESR at the output. With the recommended output
capacitors they are not necessary so R should be 0
and C should be no-pop.
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