參數(shù)資料
型號(hào)： SC486
廠商： Semtech Corporation
英文描述： Complete DDR1/2/3 Memory Power Supply
中文描述： 完全DDR1/2/3內(nèi)存供電
文件頁數(shù)： 10/26頁
文件大?。?/td> 382K
代理商： SC486
10
2006 Semtech Corp.
www.semtech.com
SC486
POWER MANAGEMENT
Application Information
+5V Bias Supply
The SC486 requires an external +5V bias supply in
addition to the battery. This is connected to VDDP for
the VDDQ switching drive power and via an RC filter to
VCCA for the chip supply. If stand-alone capability is
required, the +5V supply can be generated with an
external linear regulator.
VTTIN Supply
The VTTIN pins provide the input power for the high side
(sourcing) section of the VTT LDO. These pins should be
decoupled to PGND2. If the output capacitors for the
input supply for VTTIN (whether it is VDDQ or a different
supply) are not close to the chip, additional local bulk
capacitance may be required.
Grounding
The SC486 has three ground connections, VSSA, PGND1
and PGND2 (2 pins). These should all be starred together
at the thermal pad under the device, which in turn will be
connected to the ground plane using multiple vias. VSSA
is the controller ground reference, to avoid interference
between the power and reference sections. PGND1 is
the power ground connection for the switching
controller for VDDQ. PGND2 is the power ground
connection for the sink-source LDO for VTT. All external
components referenced to VSSA in the schematic should
be connected directly to the VSSA trace. The supply
decoupling capacitor should be tied between VCCA and
VSSA. A 10
resistor should be used to decouple the
VCCA supply from the main VDDP supply. The VDDP
input provides power to the upper and lower gate
drivers of the switching supply. A decoupling capacitor
with no series resistor between VDDP and 5V is required.
See layout guidelines for more details.
Pseudo-fixed Frequency Constant On-Time PWM
Controller (VDDQ)
The PWM control architecture consists of a constant on-
time, pseudo fixed frequency PWM controller (see Figure
1, SC486 Block Diagram). The output ripple voltage
developed across the output filter capacitor’s ESR
provides the PWM ramp signal eliminating the need for a
current sense resistor. The high-side switch on-time is
determined by a one-shot whose period is directly
proportional to output voltage and inversely proportional
to input voltage. A second one-shot sets the minimum
off-time which is typically 400ns.
On-Time One-Shot (t
)
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage-proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the
high-side switch directly proportional to output voltage
and inversely proportional to input voltage. This
implementation results in a nearly constant switching
frequency without the need for a clock generator.
ns
50
V
V
)
10
x
37
R
(
10
x
3
t
IN
OUT
3
TON
12
ON
+
+
=
R
is a resistor connected from the input supply to the
TON
pin. Due to the high impedance of this resistor, the
TON pin should always be bypassed to VSSA using a 1nF
ceramic capacitor.
EN/PSV: Enable, PSAVE and Soft Discharge
The EN/PSV pin enables the VDDQ (2.5V or 1.8V) output
and the REF output. VTTEN enables the VTT (1.25V or
0.9V) output provided that VDDQ is present. See Enable
Control Logic on Page 9.
When EN/PSV is pulled high the VDDQ controller is
enabled and power save will also be enabled. When the
EN/PSV pin is tri-stated (allowed to float, a 10nF
capacitor is required in this instance), an internal pull-up
will activate the VDDQ controller and power save will be
disabled. If PSAVE is enabled, the SC486 PSAVE
comparator will look for the inductor current to cross
zero on eight consecutive switching cycles by comparing
the phase node (LX) to PGND1. Once observed, the
controller will enter power save and turn off the low side
MOSFET when the current crosses zero. To improve light-
load efficiency and add hysteresis, the on-time is
increased by 50% in power save. The efficiency
improvement at light-loads more than offsets the
disadvantage of slightly higher output ripple. If the
inductor current does not cross zero on any switching
cycle, the controller will immediately exit power save. Since
the controller counts zero crossings, the converter can
sink current as long as the current does not cross zero
on eight consecutive cycles. This allows the output
voltage to recover quickly in response to negative load
steps even when psave is enabled.
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