參數(shù)資料
型號: SC480
廠商: Semtech Corporation
英文描述: Complete DDR1/2/3 Memory Power Supply
中文描述: 完全DDR1/2/3內存供電
文件頁數(shù): 8/25頁
文件大?。?/td> 858K
代理商: SC480
8
2006 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
Pin Description (Cont.)
SC480
Enable Pin Status
Output Status
EN/PSV
(1)
VTTEN
VDDQ
(3)
VTT
(2)
REF
(2)
0
0
OFF, Discharged
(2)(3)
OFF, Discharged
(2)
OFF, Discharged
(2)
0
1
OFF, Discharged
(2)(3)
OFF, Discharged
(2)
OFF, Discharged
(2)
1
0
ON
OFF, High Impedance
ON
1
1
ON
ON
ON
Notes:
1) EN/PSV = 1 = EN/PSV high or
fl
oating.
2) Typical discharge resistances: VTT = 0.25
Ω
. REF = 8
Ω
.
3) VDDQ is discharged via external series resistance which must be added to SC480 internal discharge resistance to calculate discharge times.
This is separate from any external load on VDDQ.
Enable Control Logic
The FB pin can be con
fi
gured for
fi
xed or adjustable output voltage as shown.
FB Con
fi
guration Table
FB
VDDQ(V)
VREF & VTT (V)
Note
GND
2.5
VDDQS/2
DDR1
VCCA
1.8
VDDQS/2
DDR2
FB Resistors
Adjustable
VDDQS/2
1.5V < VDDQ < 3.0V
16
ILIM
Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source
for resistor sensing through a threshold sensing resistor.
17,18
PGND1
Power ground for VDDQ switching circuits. Connect to thermal pad and ground plane.
19
DL
Gate drive output for the low side MOSFET switch.
20
LX
Phase node - the junction between the top and bottom FETs and the output inductor.
21
DH
Gate drive output for the high side MOSFET switch.
22
BST
Boost capacitor connection for the high side gate drive.
23
VTTIN
Input supply for the high side switch for VTT regulator. Decouple with a 1
μ
F capacitor to
PGND2.
24
VTT
Output of the linear regulator. Decouple with two (minimum) 10
μ
F ceramic capacitors to
PGND2, locating them directly across pins 24 and 1.
T
THERMAL
PAD
Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected
internally.
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