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參數(shù)資料
| 型號： | SC475A |
| 廠商： | Semtech Corporation |
| 英文描述： | Synchronous Buck Controller with Dual-Level VOUT Transition Support |
| 中文描述： | 同步降壓控制器與雙級VOUT電源支持過渡 |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 603K |
| 代理商： | SC475A |
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21
2006 Semtech Corp.
SC475A
www.semtech.com
POWER MANAGEMENT
Applications Information
(continued)
Looking at the control section
fi
rst, locate all components
referenced to RTN on the schematic and place these
components near the chip and on the same side if
possible. Connect RTN using a wide trace. Very little
current
fl
ows in the RTN path and therefore large areas
of copper are not needed. Connect the RTN pin directly to
the thermal pad under the device as the only connection
between RTN and GND.
The chip supply decoupling capacitor (VCC/GND) should
be located near to the pins. Since the DL pin is directly
between VCC and GND, and the DL trace must be a wide,
direct trace, the VCC decoupling capacitor is best placed
on the opposite side of the PCB, routed with traces as short
as possible and using at least two vias when connecting
through the PCB.
There are two sensitive, feedback-related pins at the chip:
VOUT and FB. Proper routing is needed to keep noise
away from these signals. All components connected to
FB should be located directly at the chip, and the copper
area of the FB node minimized. The VOUT trace that
feeds into the VOUT pin, which also feeds the FB resistor
divider, must be kept far away from noise sources such
as switching nodes, inductors and gate drives. Route the
VOUT trace in a quiet layer if possible, from the output
capacitor back to the chip.
For the switcher power section, there are a few key
guidelines to follow:
1) There should be a very small input loop between
the input capacitors, MOSFETs, inductor, and output
capacitors. Locate the input decoupling capacitors
directly at the MOSFETs.
2) The phase node should be a large copper pour, but still
compact since this is the noisiest node.
3) The power GND connection between the input
capacitors, low-side MOSFET, and output capacitors
should be as small as is practical, with wide traces or
planes.
4) The impedance of the power GND connection
between the low-side MOSFET and the GND pin should
be minimized. This connection must carry the DL drive
current, which has high peaks at both rising and falling
edges. Use mulitple layers and multiple vias to minimize
impedance, and keep the distance as short as practical.
Finally, connecting the control and switcher power sections
should be accomplished as follows:
1) Route the VOUT/FB feedback traces in a “quiet” layer,
away from noise sources.
2) Route DL, DH and LX (low side FET gate drive, high side
FET gate drive and phase node) to the chip using wide
traces, with multiple vias if using more than one layer.
These connections are to be as short as possible for loop
minimization, with a length to width ratio less than 20:1
to minimize impedance. DL is the most critical gate drive,
with power GND as its return path. LX is the noisiest node
in the circuit, switching between VBAT and ground at high
frequencies, thus should be kept as short as practical. DH
has LX as its return path. DL, DH, LX, and BST are high-
noise signals and should be kept well away from sensitive
signals, particularly FB and VOUT.
3) BST is also a noisy node and should be kept as short
as possible. The high-side DH driver is relies on the boost
capacitor to provide the DH drive current, so the boost
capacitor must be placed near the IC and connect to the
BST and LX pins using short, wide traces to minimize
impedance.
4) Connect the GND pin on the chip to the VCC decoupling
capacitor and then drop vias directly to the ground plane.
Locate the current limit resistor RLIM at the chip with a
kelvin connection to the drain of the lower MOSFET at the
phase node, and minimize the copper area of the ILIM
trace.
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