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參數資料
| 型號： | SC475A |
| 廠商： | Semtech Corporation |
| 英文描述： | Synchronous Buck Controller with Dual-Level VOUT Transition Support |
| 中文描述： | 同步降壓控制器與雙級VOUT電源支持過渡 |
| 文件頁數： | 20/27頁 |
| 文件大?。?/td> | 603K |
| 代理商： | SC475A |
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20
2006 Semtech Corp.
SC475A
www.semtech.com
POWER MANAGEMENT
Applications Information
(continued)
Passive droop minimizes the required output capacitance
because the voltage excursions due to load steps are
reduced.
The use of 1% feedback resistors contributes typically
1% error. If tighter DC accuracy is required use 0.1%
resistors.
The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage. The output ESR also affects the ripple and thus
the DC output voltage.
Switching Frequency Variations
The switching frequency will vary somewhat due to line
and load conditions. The line variations are a result
of a
fi
xed offset in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VBAT increases, these factors make the actual DH on-time
slightly longer than the idealized on-time. The net effect
is that frequency tends to fall slightly with increasing input
voltage.
The load variations are due to losses in the power train
from IR drop and switching losses. For a conventional
PWM constant-frequency topology, as load increases
the duty cycle also increases slightly to compensate for
IR and switching losses in the MOSFETs and inductor. A
constant on-time topology must also overcome the same
losses by increasing the duty cycle (more time is spent
drawing energy from VBAT as losses increase). Since the
on-time is constant for a given VOUT/VBAT combination,
the way to increase duty cycle is to gradually shorten
the off-time. The net effect is that switching frequency
increases slightly with increasing load.
Layout Guidelines
One or more ground planes are recommended to minimize
the effect of switching noise and copper losses and to
maximize heat removal. The analog ground reference,
RTN, should connect directly to the thermal pad, which
in turn connects to the ground plane through preferably
one large via. There should be a RTN plane or copper
are near the chip; all components that are referenced to
RTN should connect to this plane directly, not through the
ground plane, and located on the chip side of the PCB if
possible.
GND should be a separate plane which is not used for
routing analog traces. The VCC input provides power to
the internal analog circuits and the upper and lower gate
drivers.
The VCC supply decoupling capacitor should be tied
between VCC and GND with short traces. All power GND
connections should connect directly to this plane with
special attention given to avoiding indirect connections
between RTN and GND which will create ground loops.
As mentioned above, the RTN plane must be connected to
the GND plane at the chip near the RTN/GND pins.
The switcher power section should connect directly to the
ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses. Make all the power connections on
one side of the PCB using wide copper
fi
lled areas if
possible. Do not use “minimum” land patterns for power
components. Minimize trace lengths and maximize trace
widths between the gate drivers and the gates of the
MOSFETs to reduce parasitic impedances (and MOSFET
switching losses); the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive
signals. Use multiple vias as required by current handling
requirement (and to reduce parasitic) if routed on more
than one layer.
For an accurate ILIM current sense connection, connect
the ILIM trace to the current sense element (MOSFET or
resistor) directly at the pin of the element, and route that
trace over to the ILIM resistor on another layer if needed.
The layout can be generally considered in two parts; the
analog control section referenced to RTN, and the switcher
power section referenced to GND.
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