參數(shù)資料
型號: SC16C652IB48
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual UART with 32 bytes of transmit and receive FIFOs
中文描述: 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, SOT313-2, LQFP-48
文件頁數(shù): 21/41頁
文件大?。?/td> 575K
代理商: SC16C652IB48
Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 — 20 June 2003
21 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 16:
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
LCR[5-3]
Programs the parity conditions (see
Table 17
).
LCR[2]
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see
Table 18
).
Logic 0 or cleared = default condition.
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 19
).
Logic 0 or cleared = default condition.
6
5-3
2
1-0
Table 17:
LCR[5]
X
X
0
0
1
LCR[5-3] parity selection
LCR[4]
X
0
1
0
1
LCR[3]
0
1
1
1
1
Parity selection
no parity
ODD parity
EVEN parity
forced parity ‘1’
forced parity ‘0’
Table 18:
LCR[2]
0
1
1
LCR[2] stop bit length
Word length
5, 6, 7, 8
5
6, 7, 8
Stop bit length (bit times)
1
1-
1
2
2
Table 19:
LCR[1]
0
0
1
1
LCR[1-0] word length
LCR[0]
0
1
0
1
Word length
5
6
7
8
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