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參數(shù)資料
| 型號： | SC16C652IB48 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Dual UART with 32 bytes of transmit and receive FIFOs |
| 中文描述： | 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, SOT313-2, LQFP-48 |
| 文件頁數(shù)： | 18/41頁 |
| 文件大小： | 575K |
| 代理商： | SC16C652IB48 |
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Philips Semiconductors
SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Product data
Rev. 04 — 20 June 2003
18 of 41
9397 750 11634
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.3.2
FIFO mode
Table 11:
Bit
7-6
FIFO Control Register bits description
Symbol
Description
FCR[7]
(MSB),
FCR[6]
(LSB)
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to
Table 12
.
FCR[5]
(MSB),
FCR[4]
(LSB)
number of characters in FIFO drops below the selected trigger level.
Refer to
Table 13
.
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C652 is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY
pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after
the first character is loaded into the transmit holding register.
Receive operation in mode ‘0’:
When the SC16C652 is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode ‘1’:
When the SC16C652 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a logic 0 when the
trigger level has been reached.
Receive operation in mode ‘1’:
When the SC16C652 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
FCR[2]
XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
5-4
Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C652 will issue a transmit empty interrupt when the
3
2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C652IB48,128 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C652IB48,151 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C652IB48,157 | 功能描述:UART 接口集成電路 16C 2.5V-5V 2CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C654 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C654B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder |
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