參數(shù)資料
型號: SC16C652B
廠商: NXP Semiconductors N.V.
英文描述: 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
中文描述: 5V的,3.3V和2.5V雙,5兆的UART /秒(最大),32字節(jié)的FIFO和紅外線(IrDA)編碼器/解碼器
文件頁數(shù): 9/44頁
文件大?。?/td> 205K
代理商: SC16C652B
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Product data
Rev. 03 — 10 December 2004
9 of 44
9397 750 14452
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.2 Internal registers
The SC16C652B provides two sets of internal registers (A and B) consisting of
17 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in
Table 4
. The UART registers function as data
holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO
control register (FCR), line status and control registers (LCR/LSR), modem status
and control registers (MCR/MSR), programmable data rate (clock) control registers
(DLL/DLM), and a user accessible scratchpad register (SPR).
[1]
[2]
[3]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF(HEX)’.
6.3 FIFO operation
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C652B provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C2550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
a time-out function to ensure data is delivered to the external CPU. An interrupt is
generated whenever the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger level has not been reached.
Table 4:
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
[1]
0
0
0
Receive Holding Register
0
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
0
1
1
Line Control Register
1
0
0
Modem Control Register
1
0
1
Line Status Register
1
1
0
Modem Status Register
1
1
1
Scratchpad Register
Baud rate register set (DLL/DLM)
[2]
0
0
0
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)
[3]
0
1
0
Enhanced Feature Register
1
0
0
Xon1 word
1
0
1
Xon2 word
1
1
0
Xoff1 word
1
1
1
Xoff2 word
Internal registers decoding
A0
READ mode
A1
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
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