參數(shù)資料
型號: SC16C652B
廠商: NXP Semiconductors N.V.
英文描述: 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
中文描述: 5V的,3.3V和2.5V雙,5兆的UART /秒(最大),32字節(jié)的FIFO和紅外線(IrDA)編碼器/解碼器
文件頁數(shù): 17/44頁
文件大?。?/td> 205K
代理商: SC16C652B
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Product data
Rev. 03 — 10 December 2004
17 of 44
9397 750 14452
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.2.1
IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit
and the interrupt will be cleared when the FIFO drops below the trigger level.
The receive data ready bit (LSR[0]) is set as soon as a character is transferred
from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is
empty.
When the Transmit FIFO and interrupts are enabled, an interrupt is generated
when the transmit FIFO is empty due to the unloading of the data by the TSR and
UART for transmission via the transmission media. The interrupt is cleared either
by reading the ISR register, or by loading the THR with new data characters.
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued
whenever a receive data error condition exists as reflected in
LSR[1:4].
Logic 0 = Disable the receiver line status interrupt (normal
default condition).
Logic 1 = Enable the receiver line status interrupt.
Transmit Holding Register interrupt. In the 16C450 mode, this
interrupt will be issued whenever the THR is empty, and is
associated with LSR[5]. In the FIFO modes, this interrupt will be
issued whenever the FIFO is empty.
Logic 0 = Disable the Transmit Holding Register Empty (TXRDY)
interrupt (normal default condition).
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
Receive Holding Register. In the 16C450 mode, this interrupt will
be issued when the RHR has data, or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued when the
FIFO has reached the programmed trigger level or is cleared when
the FIFO drops below the trigger level.
Logic 0 = Disable the receiver ready (ISR level 2, RXRDY)
interrupt (normal default condition).
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
1
IER[1]
0
IER[0]
Table 10:
Bit
Interrupt Enable Register bits description
…continued
Symbol
Description
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SC16C652BIB48151 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: