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參數(shù)資料
| 型號： | SC16C550BIBS,157 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 46/48頁 |
| 文件大小： | 0K |
| 描述： | IC UART SOT617-1 |
| 標(biāo)準(zhǔn)包裝： | 2,450 |
| 特點： | 可編程 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-HVQFN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 935279497157 SC16C550BIBS SC16C550BIBS-ND |
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SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
7 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
DSR[2]
41
39
37
25
I
Data set ready. DSR is a modem status signal. Its
condition can be checked by reading bit 5 (DSR) of the
Modem Status Register. Bit 1 (DSR) of the Modem Status
Register indicates DSR has changed levels since the last
read from the Modem Status Register. If the modem status
interrupt is enabled when DSR changes levels, an interrupt
is generated.
DTR
37
33
22
O
Data terminal ready. When active (LOW), DTR informs a
modem or data set that the UART is ready to establish
communication. DTR is placed in the active level by setting
the DTR bit of the Modem Control Register. DTR is placed
in the inactive level either as a result of a Master Reset,
during loopback mode operation, or clearing the DTR bit.
INT
33
30
20
O
Interrupt. When active (HIGH), INT informs the CPU that
the UART has an interrupt to be serviced. Four conditions
that cause an interrupt to be issued are: a receiver error,
received data that is available or timed out (FIFO mode
only), an empty Transmitter Holding Register or an
enabled modem status interrupt. INT is reset (deactivated)
either when the interrupt is serviced or as a result of a
Master Reset.
n.c.
1, 12,
23, 34
1, 6, 13,
21, 25,
36, 37,
48
-
2, 15, 16
-
not connected
OUT1
38
34
-
O
Outputs 1 and 2. These are user-designated output
terminals that are set to the active (LOW) level by setting
respective Modem Control Register (MCR) bits (OUT1 and
OUT2). OUT1 and OUT2 are set to inactive the (HIGH)
level as a result of Master Reset, during loopback mode
operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of
the MCR.
OUT2
35
31
-
RCLK
10
5
9
-
I
Receiver clock. RCLK is the 16
× baud rate clock for the
receiver section of the UART. In the HVQFN32 package,
BAUDOUT and RCLK are bonded internally.
IOR
25
20
22
-
I
Read inputs. When either IOR or IOR is active (LOW or
HIGH, respectively) while the UART is selected, the CPU
is allowed to read status information or data from a
selected UART register. Only one of these inputs is
required for the transfer of data during a read operation;
the other input should be tied to its inactive level (that is,
IOR tied LOW or IOR tied HIGH).
24
19
21
14
RESET
39
35
23
I
Master reset. When active (HIGH), RESET clears most
UART registers and sets the levels of various output
signals.
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
PLCC44 LQFP48 DIP40 HVQFN32
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C550BIBS-F | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550BIBS-S | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550BIN40 | 制造商:NXP Semiconductors 功能描述:UART 16BYTE FIFO 16C550 DIP40 |
| SC16C550BIN40,112 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550IA44 | 制造商:NXP Semiconductors 功能描述:UART 16BYTE FIFO 16C550 PLCC44 |
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