- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11830 > SC16C550BIBS,151 (NXP Semiconductors)IC UART SINGLE W/FIFO 32-HVQFN PDF資料下載
參數(shù)資料
| 型號： | SC16C550BIBS,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SINGLE W/FIFO 32-HVQFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 特點： | 可編程 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-HVQFN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 568-3263 935279497151 SC16C550BIBS-S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
26 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C550B and the CPU.
Table 20.
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when LSR register is read.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the transmit holding register and the transmit shift register are
both empty. It is reset to logic 0 whenever either the THR or TSR contains a data
character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and
transmit shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter
holding register by the CPU. In the FIFO mode, this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO.
3
LSR[3]
Framing error.
logic 0 = no framing error (normal default condition)
logic 1 = framing error. The receive character did not have a valid stop bit(s). In
the FIFO mode, this error is associated with the character at the top of the
FIFO.
2
LSR[2]
Parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with the
character at the top of the FIFO.
1
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error. A data overrun error occurred in the receive shift
register. This happens when additional data arrives while the FIFO is full. In
this case, the previous data in the shift register is overwritten. Note that under
this condition, the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
0
LSR[0]
Receive data ready.
logic 0 = no data in receive holding register or FIFO (normal default condition)
logic 1 = data has been received and is saved in the receive holding register or
FIFO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATMEGA168-15AZ | MCU AVR 16K FLASH 15MHZ 32-TQFP |
| SC16C550BIBS,128 | IC UART SOT617-1 |
| XR17C158CV-F | IC UART PCI BUS 5V OCTAL 144LQFP |
| XR17D158CV-F | IC UART PCI BUS OCTAL 144LQFP |
| ATMEGA168-15MZ | MCU AVR 16K FLASH 15MHZ 32-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C550BIBS-F | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550BIBS-S | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550BIN40 | 制造商:NXP Semiconductors 功能描述:UART 16BYTE FIFO 16C550 DIP40 |
| SC16C550BIN40,112 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550IA44 | 制造商:NXP Semiconductors 功能描述:UART 16BYTE FIFO 16C550 PLCC44 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。